Semiconductor device

Patent metadata

Field	Value
Publication number	US-2023116461-A1
Application number	US-202217876109-A
Country	US
Kind code	A1
Filing date	Jul 28, 2022
Priority date	Oct 8, 2021
Publication date	Apr 13, 2023
Grant date	—

Abstract

A semiconductor device includes a first gate electrode and a second gate electrode which are each on a substrate and extend in a first direction, first and second source/drain patterns spaced apart from the first and second gate electrodes in a second direction which crosses the first direction, and an active contact in common connection with top surfaces of the first source/drain pattern and the second source/drain pattern. The active contact comprises a first portion on the first source/drain pattern and a second portion on the second source/drain pattern. The device includes an insulating separation pattern which extends in the second direction to separate the first gate electrode from the second gate electrode, and the active contact comprises a third portion which extends to a region below a bottom surface of the insulating separation pattern to connect the first and second portions of the active contact to each other.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first gate electrode and a second gate electrode each on a substrate, wherein the first gate electrode and the second gate electrode extend in a first direction, and there is a space between the first gate electrode and the second gate electrode in the first direction; a first source/drain pattern, wherein there is a space between the first source/drain pattern and the first gate electrode in a second direction which crosses the first direction; a second source/drain pattern, wherein there is a space between the second source/drain pattern and the second gate electrode in the second direction; an active contact which extends in the first direction and is in common connection with a top surface of the first source/drain pattern and a top surface of the second source/drain pattern, the active contact comprising a first portion on the first source/drain pattern and a second portion on the second source/drain pattern; and an insulating separation pattern which extends in the second direction and separates the first gate electrode from the second gate electrode, wherein the active contact further comprises a third portion which extends to a region below a bottom surface of the insulating separation pattern and connects the first and second portions of the active contact to each other.

2 . The semiconductor device of claim 1 , wherein the bottom surface of the insulating separation pattern is higher than a bottom surface of the first portion of the active contact on the first source/drain pattern and a bottom surface of the second portion of the active contact on the second source/drain pattern.

3 . The semiconductor device of claim 1 , wherein a bottom surface of the third portion of the active contact is lower than a bottom surface of the first portion of the active contact and a bottom surface of the second portion of the active contact.

4 . The semiconductor device of claim 1 , wherein a bottom surface of the third portion of the active contact is lower than a bottom surface of the first source/drain pattern and a bottom surface of the second source/drain pattern.

5 . The semiconductor device of claim 1 , further comprising an interlayer insulating layer which covers a side surface of the active contact,
wherein the insulating separation pattern comprises a material which is different than a material of the interlayer insulating layer.

6 . The semiconductor device of claim 5 , wherein the insulating separation pattern comprises at least one of SiON, SiCN, SiCON, and SiN.

7 . The semiconductor device of claim 1 , wherein the insulating separation pattern is in contact with a side surface of the first gate electrode and a side surface of the second gate electrode.

8 . The semiconductor device of claim 1 , wherein the insulating separation pattern comprises:
a first portion which covers a top surface of the active contact; and a second portion which extends into a region between the first and second gate electrodes, wherein a bottom surface of the second portion of the insulating separation pattern is lower than a bottom surface of the first portion of the insulating separation pattern.

9 . The semiconductor device of claim 8 , further comprising a third gate electrode and a fourth gate electrode each on the substrate, wherein the third gate electrode and the fourth gate electrode extend in the first direction, and there is a space between the third gate electrode and the fourth gate electrode in the first direction,
wherein the insulating separation pattern further comprises a third portion which extends into a region between the third and fourth gate electrodes, the first portion of the insulating separation pattern is between the second and third portions of the insulating separation pattern, and a bottom surface of the third portion of the insulating separation pattern is lower than the bottom surface of the first portion of the insulating separation pattern.

10 . The semiconductor device of claim 8 , wherein the first portion of the insulating separation pattern overlaps the third portion of the active contact.

11 . The semiconductor device of claim 1 , wherein the substrate comprises a PMOSFET region, an NMOSFET region, and a separation region between the PMOSFET region and the NMOSFET region,
the first gate electrode is on the PMOSFET region, the second gate electrode is on the NMOSFET region, and the insulating separation pattern is on the separation region.

12 . A semiconductor device, comprising:
a first gate electrode and a second gate electrode each on a substrate, wherein the first gate electrode and the second gate electrode extend in a first direction, and there is a space between the first gate electrode and the second gate electrode in the first direction; a first source/drain pattern, wherein there is a space between the first source/drain pattern and the first gate electrode in a second direction which crosses the first direction; a second source/drain pattern, wherein there is a space between the second source/drain pattern and the second gate electrode in the second direction; an active contact which extends in the first direction and is connected in common to top surfaces of the first and second source/drain patterns; and an insulating separation pattern which extends in the second direction to separate the first gate electrode from the second gate electrode, wherein the insulating separation pattern comprises:
a first portion which covers a top surface of the active contact; and
a second portion which extends into a region between the first and second gate electrodes, and
wherein a bottom surface of the second portion of the insulating separation pattern is lower than a bottom surface of the first portion of the insulating separation pattern.

13 . The semiconductor device of claim 12 , further comprising a third gate electrode and a fourth gate electrode each on the substrate, wherein the third gate electrode and the fourth gate electrode extend in the first direction, and there is a space between the third gate electrode and the fourth gate electrode in the first direction,
wherein the insulating separation pattern further comprises a third portion which extends into a region between the third and fourth gate electrodes, the first portion of the insulating separation pattern is between the second and third portions of the insulating separation pattern, and a bottom surface of the third portion of the insulating separation pattern is lower than the bottom surface of the first portion of the insulating separation pattern.

14 . The semiconductor device of claim 12 , wherein the active contact comprises:
a first portion on the first source/drain pattern; a second portion on the second source/drain pattern; and a third portion which extends to a region below a bottom surface of the first portion of the insulating separation pattern and connects the first and second portions of the active contact to each other.

15 . The semiconductor device of claim 14 , wherein the first portion of the insulating separation pattern overlaps a third portion of the active contact.

16 . The semiconductor device of claim 15 , wherein the bottom surface of the first portion of the insulating separation pattern is higher than a bottom surface of the first portion of the active contact on the first source/drain pattern and a bottom surface of the second portion of the active contact on the second source/drain pattern.

17 . The semiconductor device of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jongchul
• Ra Hyonwook

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10D84/83 Primary

  of only insulated-gate FETs [IGFET] · CPC title