Semiconductor memory device, method for fabricating the same and electronic system including the same

Patent metadata

Field	Value
Publication number	US-2023114139-A1
Application number	US-202217900172-A
Country	US
Kind code	A1
Filing date	Aug 31, 2022
Priority date	Oct 8, 2021
Publication date	Apr 13, 2023
Grant date	—

Abstract

A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

First claim

1 . A semiconductor memory device comprising:
a cell substrate comprising a cell array region and an extension region; a first mold structure on the cell substrate, the first mold structure comprising a plurality of first gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region; a second mold structure on the first mold structure, the second mold structure comprising a plurality of second gate electrodes sequentially stacked on the first mold structure on the cell array region and stacked in a stepwise manner on the extension region; a channel structure passing through the first mold structure and the second mold structure on the cell array region; and a cell contact structure passing through the first mold structure and the second mold structure on the extension region, wherein the cell contact structure comprises a lower conductive pattern connected to one of the plurality of first gate electrodes, an upper conductive pattern connected to one of the plurality of second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

2 . The semiconductor memory device of claim 1 , further comprising:
an insulating ring between the cell contact structure and each of the plurality of first gate electrodes and between the cell contact structure and each of the plurality of second gate electrodes.

3 . The semiconductor memory device of claim 1 , wherein
the cell contact structure comprises a first extension portion under the first mold structure, a second extension portion between the first mold structure and the second mold structure, a third extension portion on the second mold structure, a first through portion passing through the first mold structure and connecting the first extension portion to the second extension portion, and a second through portion passing through the second mold structure and connecting the second extension portion to the third extension portion, and a width of the first extension portion, a width of the second extension portion, and a width of the third extension portion each are greater than a width of the first through portion and a width of the second through portion.

4 . The semiconductor memory device of claim 3 , wherein
the lower conductive pattern is in the first extension portion, the second extension portion, the first through portion, and the second through portion, the upper conductive pattern is in the third extension portion, and at least a part of the insulating pattern is in the second through portion and separates the lower conductive pattern from the upper conductive pattern.

5 . The semiconductor memory device of claim 3 , further comprising:
a first stopper layer between the cell substrate and the first mold structure; and a second stopper layer between the first mold structure and the second mold structure, wherein an upper surface of the first extension portion is defined by a bottom surface of the first stopper layer, and an upper surface of the second extension portion is defined by a bottom surface of the second stopper layer.

6 . The semiconductor memory device of claim 1 , further comprising:
a first interlayer insulating layer on the cell substrate, the first interlayer insulating layer covering the first mold structure; a second interlayer insulating layer on the first interlayer insulating layer, the second interlayer insulating layer covering the second mold structure; and a substrate contact structure passing through the first interlayer insulating layer and the second interlayer insulating layer, wherein the substrate contact structure is connected to the cell substrate.

7 . The semiconductor memory device of claim 1 , further comprising:
a through via structure, wherein the cell substrate includes a through region, each of the first mold structure and the second mold structure comprises a plurality of mold sacrificial layers sequentially stacked on the cell substrate on the through region, the through via structure passes through the first mold structure and the second mold structure on the through region.

8 . The semiconductor memory device of claim 1 , further comprising:
a third mold structure between the first mold structure and the second mold structure on the extension region, wherein the third mold structure comprises a plurality of mold sacrificial layers sequentially stacked on the first mold structure, the lower conductive pattern passes through the third mold structure, and the lower conductive pattern is connected to one of the plurality of first gate electrodes.

9 . The semiconductor memory device of claim 1 , further comprising:
a peripheral circuit board; a peripheral circuit element on the peripheral circuit board; an inter-wiring insulating layer covering the peripheral circuit element; and a wiring structure in the inter-wiring insulating layer, the wiring structure connecting the peripheral circuit element to the cell contact structure, wherein the cell substrate is on the inter-wiring insulating layer.

10 . The semiconductor memory device of claim 9 , further comprising:
a through via structure passing through the first mold structure and the second mold structure on the extension region, wherein the through via structure connects one of the lower conductive pattern and the upper conductive pattern to the wiring structure.

11 . A semiconductor memory device comprising:
a cell substrate comprising a cell array region and an extension region; a first mold structure on the cell substrate, the first mold structure comprising a plurality of first gate electrodes sequentially stacked on the cell array region, each of the plurality of first gate electrodes comprising a first pad region in which a part of an upper surface thereof is exposed on the extension region; a second mold structure on the first mold structure, the second mold structure comprising a plurality of second gate electrodes sequentially stacked on the first mold structure, each of the plurality of second gate electrodes comprising a second pad region in which a part of an upper surface thereof is exposed on the extension region; a channel structure extending in a vertical direction intersecting an upper surface of the cell substrate on the cell array region, the channel structure passing through the first mold structure and the second mold structure; a word line cutting region extending in a first direction crossing the vertical direction to cut the first mold structure and the second mold structure; a bit line extending in a second direction crossing the first direction and the vertical direction, the bit line connected to the channel structure; a cell contact structure extending in the vertical direction on the extension region, the cell contact structure passing through the first mold structure and the second mold structure; and an insulating ring between the cell contact structure and each of the plurality of first gate electrodes and between the cell contact structure and each of the plurality of second gate electrodes, wherein the cell contact structure comprises a lower conductive pattern in contact with the pad region of a corresponding first gate electrode among the plurality of first gate electrodes, an upper conductive pattern in contact with the second pad region of a corresponding second gate electrode among the plurality of second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

12 . The semiconductor memory device of claim 11 , wherein
the cell contact structure compr

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Yong-Hoon
• Kim Joon Sung
• Sung Suk Kang
• Lee Gil Sung
• Lee Jong-Min

Classifications

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title