Integrated circuit, method for forming a layout of integrated circuit using standard cells

Patent metadata

Field	Value
Publication number	US-2023099326-A1
Application number	US-202217869797-A
Country	US
Kind code	A1
Filing date	Jul 21, 2022
Priority date	Sep 28, 2021
Publication date	Mar 30, 2023
Grant date	—

Abstract

A method for forming an integrated circuit layout including at least two standard cells having different cell heights is disclosed. The standard cells respectively have a well boundary to divide a PMOS region and an NMOS region. The standard cells are abutted side by side along their side edges in a way that the well boundaries of the cells are aligned along the row direction. The power rail and the ground rail of one of the standard cells are extended in width or length to connect to the power rail and the ground rail of the other one of the standard cells.

First claim

What is claimed is:

1 . A method for forming an integrated circuit layout, comprising:
selecting a first standard cell and a second standard cell having different cell heights, which respectively comprising:
a power rail, a ground rail, and a well boundary extending in parallel along a first direction;
two active regions of opposite conductivity types between the power rail and the ground rail and at two sides of the well boundary; and
a gate line extending along a second direction and intersecting the two active regions, wherein the first direction and the second direction are perpendicular;
abutting the first standard cell and the second standard cell side by side to form a temporary placement in a way that the well boundaries of the first standard cell and the second standard cell are aligned along the first direction; and based on the temporary placement, generating the integrated circuit layout by at least one of:
extending widths of the power rail and the ground rail of the second standard cell along the second direction until flush with edges of the power rail and the ground rail of the first standard cell along the first direction; and
extending lengths of the power rail and the ground rail of the first standard cell along the first direction until flush with edges of the power rail and the ground rail of the second standard cell along the second direction.

2 . The method according to claim 1 , wherein extending widths of the power rail and the ground rail of the second standard cell are the same.

3 . The method according to claim 1 , wherein the well boundary of each of the first standard cell and the second standard cell is overlapped with a centerline of each of the first standard cell and the second standard cell.

4 . The method according to claim 1 , wherein a centerline of the first standard cell and a centerline of the second standard cell are aligned along the first direction and are parallel to the well boundaries in the temporary placement.

5 . The method according to claim 3 , wherein a centerline of the first standard cell and a centerline of the second standard cell are offset along the first direction in the temporary placement, and extending widths of the power rail and the ground rail of the second standard cell are different.

6 . The method according to claim 1 , further comprising extending lengths of the power rail and the ground rail of the second standard cell along the first direction to fill a space between the power rail of the second standard cell and a conductive connector of the first standard cell and another space between the ground rail of the second standard cell and another conductive connector of the first standard cell.

7 . The method according to claim 1 , wherein abutting the first standard cell and the second standard cell and extending the power rails and the ground rails are performed in an electronic design automation (EDA) environment.

8 . The method according to claim 1 , wherein the first standard cell and the second standard cell further comprise, respectively, two dummy gate lines parallel to the gate line and arranged at two sides of the two active regions.

9 . The method according to claim 8 , wherein abutting the first standard cell and the second standard cell comprises combining one of the two dummy gate lines of the first standard cell and one of the two dummy gate lines of the second standard cell.

10 . The method according to claim 1 , further comprising outputting the integrated circuit layout to a set of photomasks used in a manufacturing process to form an integrated circuit chip.

11 . An integrated circuit layout, comprising:
a power rail and a ground rail extending in parallel along a first direction and respectively having a narrow portion connected to a wide portion; a first standard cell between the narrow portions of the power rail and the ground rail; and a second standard cell between the wide portions of the power rail and the ground rail and abutted to a side of the first standard cell, wherein the first standard cell and the second standard cell respectively comprise:
an upper edge overlapping the power rail, a lower edge overlapping the ground rail, and a well boundary between the upper edge and the lower edge;
two active regions of opposite conductivity types at two sides of the well boundary; and
a gate line extending between the upper edge and the lower edge along a second and intersecting the two active regions, wherein the first direction and the second direction are perpendicular,
wherein a first cell height between the upper edge and lower edge of the first standard cell and a second cell height between the upper edge and lower edge of the second standard cell are different, the well boundaries of the first standard cell and the second standard cell are aligned along the first direction.

12 . The integrated circuit layout according to claim 11 , wherein a centerline between the upper edge and the lower edge of the first standard cell and a centerline between the upper edge and the lower edge of the second standard cell are aligned along the first direction.

13 . The integrated circuit layout according to claim 12 , wherein the centerline and the well boundary of each of the first standard cell and the second standard cell are overlapped.

14 . The layout according to claim 12 , wherein the centerline and the well boundary of each of the first standard cell and the second standard cell are not overlapped.

15 . The integrated circuit layout according to claim 11 , wherein a distance between the narrow portion of the power rail and an edge of the active regions of the first standard cell close to the narrow portion and a distance between the wide portion of the power rail and an edge of the active regions of the second standard cell close to the wide portion are the same.

16 . The integrated circuit layout according to claim 11 , wherein the upper edge of the first standard cell overlaps a centerline of the narrow portion of the power rail, the lower edge of the first standard cell overlaps a centerline of the narrow portion of the ground rail.

17 . The integrated circuit layout according to claim 11 , wherein edges of the active regions of a same conductivity type of the first standard cell and the second standard cell adjacent to the well boundary are aligned along the first direction.

18 . The integrated circuit layout according to claim 11 , wherein edges of the active regions of a same conductivity type of the first standard cell and the second standard cell adjacent to the well boundary are offset along the first direction.

19 . The integrated circuit layout according to claim 11 , further comprising:
a first conductive connector extending from an edge of the narrow portion of the power rail along the second direction a first length to partially overlap one of the active regions of the first standard cell; and a second conductive connector extending from an edge of wide portion of the power rail a second length to partially overlap one of the active regions of the second standard cell, wherein the first length and the second length are different.

20 . The integrated circuit layout according to claim 11 , further comprising:
a first dummy gate line at a side of the first standard cell opposite to the second standard cell; a second dummy gate line at a side of the second standard cell opposite to the second standard cell; and a third dummy gate line between the first standard c

Assignees

• United Microelectronics Corp

Inventors

• Chen Chien-Hung
• Chen Ruei-Yau
• Wang Wei-Jen
• Wu Kun-Yuan
• Chen Chien-Fu
• Hsu Chen-Hsien

Classifications

• H10D84/981

  Power supply lines · CPC title

• H10D84/907 Primary

  CMOS gate arrays · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L27/11807 Primary

  Electricity · mapped topic