Semiconductor device

Patent metadata

Field	Value
Publication number	US-2023093818-A1
Application number	US-202217684125-A
Country	US
Kind code	A1
Filing date	Mar 1, 2022
Priority date	Sep 24, 2021
Publication date	Mar 30, 2023
Grant date	—

Abstract

A semiconductor device includes: a first semiconductor chip including a first coil that generates a magnetic field signal; a wiring board including a second coil, a third coil, and a twisted pair wiring, the second coil being disposed to face the first coil and receiving the magnetic field signal generated by the first coil, the twisted pair wiring connecting the second coil with the third coil; and a second semiconductor chip including a fourth coil disposed to face the third coil and receiving a magnetic field signal generated by the third coil.

First claim

1 . A semiconductor device comprising:
a first semiconductor chip including a first coil that generates a magnetic field signal; a wiring board including a second coil, a third coil, and a twisted pair wiring, the second coil being disposed to face the first coil and receiving the magnetic field signal generated by the first coil, the twisted pair wiring connecting the second coil with the third coil; and a second semiconductor chip including a fourth coil disposed to face the third coil and receiving a magnetic field signal generated by the third coil.

2 . The semiconductor device according to claim 1 , wherein
the twisted pair wiring includes
a first wiring layer including a plurality of first wiring patterns,
a second wiring layer including a plurality of second wiring patterns, and
a connection wiring layer formed between the first wiring layer and the second wiring layer, the connection wiring layer including a plurality of connection wiring patterns each of which connects each of the plurality of first wiring patterns with each of the plurality of second wiring patterns.

3 . The semiconductor device according to claim 2 , wherein in the second coil,
the first wiring layer includes a first coil pattern, the second wiring layer includes a second coil pattern, and the connection wiring layer includes a coil connection wiring pattern that connects the first coil pattern with the second coil pattern.

4 . The semiconductor device according to claim 2 , wherein the second wiring layer and the connection wiring layer form an integral wiring layer.

5 . The semiconductor device according to claim 2 , wherein the first wiring layer is formed on a first principal surface of a substrate,
the second wiring layer is formed on a second principal surface of the substrate on a side opposite to the first principal surface, and the connection wiring layer is formed of a plurality of through wirings formed in the substrate.

6 . A semiconductor device comprising:
a first semiconductor chip including a first coil that generates a magnetic field signal; a wiring board including a second coil and a twisted pair wiring, the second coil being disposed to face the first coil and receiving the magnetic field signal generated by the first coil, the twisted pair wiring being connected with the second coil; and a second semiconductor chip connected with the twisted pair wiring.

7 . The semiconductor device according to claim 6 , wherein the twisted pair wiring includes
a first wiring layer including a plurality of first wiring patterns, a second wiring layer including a plurality of second wiring patterns, and a connection wiring layer formed between the first wiring layer and the second wiring layer, the connection wiring layer including a plurality of connection wiring patterns each of which connects each of the plurality of first wiring patterns with each of the plurality of second wiring patterns.

8 . The semiconductor device according to claim 7 , wherein in the second coil,
the first wiring layer includes a first coil pattern, the second wiring layer includes a second coil pattern, and the connection wiring layer includes a coil connection wiring pattern that connects the first coil pattern with the second coil pattern.

9 . The semiconductor device according to claim 7 , wherein the second wiring layer and the connection wiring layer form an integral wiring layer.

10 . The semiconductor device according to claim 7 , wherein the first wiring layer is formed on a first principal surface of a substrate,
the second wiring layer is formed on a second principal surface of the substrate on a side opposite to the first principal surface, and the connection wiring layer is formed of a plurality of through wirings formed in the substrate.

11 . A semiconductor device comprising:
a first semiconductor chip; a wiring board including a first coil, a second coil, a third coil, a twisted pair wiring, and a fourth coil, the first coil being connected with the first semiconductor chip, the second coil being disposed to face the first coil and receiving a magnetic field signal generated by the first coil, the twisted pair wiring connecting the second coil with the third coil, the fourth coil receiving a magnetic field signal generated by the third coil; and a second semiconductor chip connected with the fourth coil.

12 . The semiconductor device according to claim 11 , wherein the wiring board includes a second terminal disposed at a position different from a position of a first terminal bonded to the first semiconductor chip by soldering, the second terminal being connected with the first coil without being bonded to the first semiconductor chip by soldering.

13 . The semiconductor device according to claim 11 , wherein the twisted pair wiring includes
a first wiring layer including a plurality of first wiring patterns, a second wiring layer including a plurality of second wiring patterns, and a connection wiring layer formed between the first wiring layer and the second wiring layer, the connection wiring layer including a plurality of connection wiring patterns each of which connects each of the plurality of first wiring patterns with each of the plurality of second wiring patterns.

14 . The semiconductor device according to claim 13 , wherein in the second coil,
the first wiring layer includes a first coil pattern, the second wiring layer includes a second coil pattern, and the connection wiring layer includes a coil connection wiring pattern that connects the first coil pattern with the second coil pattern.

15 . The semiconductor device according to claim 13 , wherein the second wiring layer and the connection wiring layer form an integral wiring layer.

16 . The semiconductor device according to claim 13 , wherein the first wiring layer is formed on a first principal surface of a substrate,
the second wiring layer is formed on a second principal surface of the substrate on a side opposite to the first principal surface, and the connection wiring layer is formed of a plurality of through wirings formed in the substrate.

17 . A semiconductor device comprising:
a first semiconductor chip; a wiring board including a first coil, a second coil, and a twisted pair wiring, the first coil being connected with the first semiconductor chip, the second coil being disposed to face the first coil and receiving a magnetic field signal generated by the first coil, the twisted pair wiring being connected with the second coil; and a second semiconductor chip connected with the twisted pair wiring.

18 . The semiconductor device according to claim 17 , wherein the wiring board includes a second terminal disposed at a position different from a position of a first terminal bonded to the first semiconductor chip by soldering, the second terminal being connected with the first coil without being bonded to the first semiconductor chip by soldering.

19 . The semiconductor device according to claim 17 , wherein the twisted pair wiring includes
a first wiring layer including a plurality of first wiring patterns, a second wiring layer including a plurality of second wiring patterns, and a connection wiring layer formed between the first wiring layer and the second wiring layer, the connection wiring layer including a plurality of connection wiring patterns each of which connects each of the plurality of first wiring patterns with each of the plurality of second wiring patterns.

20 . The semic

Assignees

• Toshiba Kk
• Toshiba Electronic Devices & Storage Corp

Inventors

• Murasaki Takeshi
• Arai Tadashi
• Arai Makoto
• Ootaka Shoji
• Imaizumi Yusuke

Classifications

• H10W90/293

  characterised by non-galvanic coupling between the chips, e.g. capacitive coupling · CPC title

• H10W44/203

  Electrical connections · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title