Multilayer electronic component
US-2022246343-A1 · Aug 4, 2022 · US
US2023074751A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2023074751-A1 |
| Application number | US-202217896464-A |
| Country | US |
| Kind code | A1 |
| Filing date | Aug 26, 2022 |
| Priority date | Sep 9, 2021 |
| Publication date | Mar 9, 2023 |
| Grant date | — |
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An LC circuit includes a first capacitor provided between a first connection point and a second connection point, a second capacitor provided between the second connection point and a third connection point, a third capacitor provided between the third connection point and a fourth connection point, a fourth capacitor provided between the first connection point and the third connection point, a fifth capacitor provided between the second connection point and the fourth connection point, a first inductor connected to the second connection point, and a second inductor connected to the third connection point.
Opening claim text (preview).
What is claimed is: 1 . An LC circuit comprising: a first capacitor provided between a first connection point and a second connection point; a second capacitor provided between the second connection point and a third connection point; a third capacitor provided between the third connection point and a fourth connection point; a fourth capacitor provided between the first connection point and the third connection point; a fifth capacitor provided between the second connection point and the fourth connection point; a first inductor connected to the second connection point; and a second inductor connected to the third connection point. 2 . The LC circuit according to claim 1 , wherein the first inductor is provided between the second connection point and ground, and the second inductor is provided between the third connection point and the ground. 3 . The LC circuit according to claim 2 , further comprising a third inductor provided between each of the first inductor and the second inductor and the ground. 4 . The LC circuit according to claim 1 , further comprising: a sixth capacitor connected to the second connection point and connected in parallel to the first inductor; and a seventh capacitor connected to the third connection point and connected in parallel to the second inductor. 5 . The LC circuit according to claim 1 , wherein the first connection point is connected to a first signal port for signal inputting or outputting, and the fourth connection point is connected to a second signal port for the signal inputting or outputting. 6 . The LC circuit according to claim 5 , wherein the first to fourth connection points are sequentially provided on a signal path connecting the first signal port and the second signal port. 7 . The LC circuit according to claim 5 , wherein another circuit is provided at least one of between the first connection point and the first signal port or between the fourth connection point and the second signal port. 8 . The LC circuit according to claim 1 , further comprising a stack for integrating the first to fifth capacitors and the first and second inductors, the stack including a plurality of dielectric layers and conductor layers that are stacked. 9 . The LC circuit according to claim 8 , wherein the plurality of conductor layers include a plurality of capacitor conductor layers for constituting the first to fifth capacitors and a plurality of inductor conductor layers for constituting the first and second inductors. 10 . The LC circuit according to claim 9 , wherein the plurality of capacitor conductor layers include two capacitor conductor layers disposed at a same position in a stacking direction of the plurality of dielectric layers, and the two capacitor conductor layers are point symmetric to each other. 11 . The LC circuit according to claim 9 , wherein the plurality of inductor conductor layers include two inductor conductor layers disposed at a same position in a stacking direction of the plurality of dielectric layers, and the two inductor conductor layers are point symmetric to each other. 12 . A filter comprising: a first signal port and a second signal port each used for signal inputting or outputting; a signal path that connects the first signal port and the second signal port and on which a first connection point, a second connection point, a third connection point, and a fourth connection point are sequentially provided; a first capacitor provided between the second connection point and the third connection point; a second capacitor provided between the first connection point and the third connection point; a third capacitor provided between the second connection point and the fourth connection point; a first inductor connected to the second connection point; and a second inductor connected to the third connection point. 13 . The filter according to claim 12 , wherein the first inductor is provided between the second connection point and ground, and the second inductor is provided between the third connection point and the ground. 14 . The filter according to claim 13 , further comprising a third inductor provided between each of the first inductor and the second inductor and the ground. 15 . The filter according to claim 12 , further comprising: a fourth capacitor provided between the first connection point and the second connection point; and a fifth capacitor provided between the third connection point and the fourth connection point. 16 . The filter according to claim 15 , wherein the first to fifth capacitors and the first and second inductors constitute a high-pass filter. 17 . The filter according to claim 15 , wherein another circuit is provided at least one of between the first connection point and the first signal port or between the fourth connection point and the second signal port. 18 . The filter according to claim 17 , wherein the first to fifth capacitors and the first and second inductors constitute a high-pass filter, and the other circuit is a low-pass filter. 19 . The filter according to claim 12 , further comprising: a sixth capacitor connected to the second connection point and connected in parallel to the first inductor; and a seventh capacitor connected to the third connection point and connected in parallel to the second inductor. 20 . The filter according to claim 12 , further comprising a stack for integrating the first to third capacitors and the first and second inductors, the stack including a plurality of dielectric layers and conductor layers that are stacked. 21 . The filter according to claim 20 , wherein the plurality of conductor layers include a plurality of capacitor conductor layers for constituting the first to third capacitors and a plurality of inductor conductor layers for constituting the first and second inductors. 22 . The filter according to claim 21 , wherein the plurality of capacitor conductor layers include two capacitor conductor layers disposed at a same position in a stacking direction of the plurality of dielectric layers, and the two capacitor conductor layers are point symmetric to each other. 23 . The filter according to claim 21 , wherein the plurality of inductor conductor layers include two inductor conductor layers disposed at a same position in a stacking direction of the plurality of dielectric layers, and the two inductor conductor layers are point symmetric to each other.
Multilayer, e.g. LTCC, HTCC, green sheets · CPC title
Comprising bridging elements, i.e. elements in a series path without own reference to ground and spanning branching nodes of another series path (H03H7/07 takes precedence) · CPC title
comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title
Duplexers · CPC title
Parallel LC in series path (H03H7/1783 takes precedence) · CPC title
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