Lateral bipolar transistor

Patent metadata

Field	Value
Publication number	US-2023061717-A1
Application number	US-202117533805-A
Country	US
Kind code	A1
Filing date	Nov 23, 2021
Priority date	Sep 1, 2021
Publication date	Mar 2, 2023
Grant date	—

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region within a semiconductor substrate material; a shallow trench isolation structure extending into the semiconductor substrate material and bounding the extrinsic base region; an emitter region adjacent to the shallow trench isolation structure and on a side of the extrinsic base region; and a collector region adjacent to the shallow trench isolation structure and on an opposing side of the extrinsic base region.

First claim

What is claimed:

1 . A structure comprising:
an extrinsic base region within a semiconductor substrate material; a shallow trench isolation structure extending into the semiconductor substrate material and bounding the extrinsic base region; an emitter region adjacent to the shallow trench isolation structure and on a side of the extrinsic base region; and a collector region adjacent to the shallow trench isolation structure and on an opposing side of the extrinsic base region.

2 . The structure of claim 1 , wherein the extrinsic base region comprises a p-well region extending below the shallow trench isolation structure.

3 . The structure of claim 2 , wherein the emitter region comprises an n-well region extending underneath the shallow trench isolation structure which contacts the p-well region.

4 . The structure of claim 3 , wherein a p-n junction is at an interface of the n-well region contacting the p-well region between the extrinsic base region and the emitter region.

5 . The structure of claim 2 , wherein the collector region comprises an N+ well region adjacent to the shallow trench isolation structure and a N− well extending underneath the shallow trench isolation structure and contacting the p-well region.

6 . The structure of claim 5 , wherein a p-n junction is at an interface of the N− well region contacting the p-well region between the extrinsic base region and the collector region.

7 . The structure of claim 1 , wherein the extrinsic base region, the emitter region and the collector region are isolated in the semiconductor substrate material by a deep n-well and n-wells contacting the deep n-well.

8 . The structure of claim 1 , wherein the extrinsic base region, the emitter region and the collector region are isolated in the semiconductor substrate material by a deep n-well and deep trench isolation structures contacting the deep n-well.

9 . The structure of claim 1 , wherein the extrinsic base region, the emitter region and the collector region comprise doped epitaxial semiconductor material adjacent to the shallow trench isolation structure.

10 . The structure of claim 9 , wherein the doped epitaxial semiconductor material of the extrinsic base region comprises P+ doped SiGe material.

11 . The structure of claim 9 , wherein the extrinsic base region, the emitter region and the collector region comprise a raised extrinsic base region, a raised emitter region and a raised collector region, respectively.

12 . A structure comprising:
a shallow trench isolation structure extending into a semiconductor substrate; an extrinsic base region within the semiconductor substrate material and extending to below the shallow trench isolation structure; an emitter region extending below the shallow trench isolation structure and contacting the extrinsic base region; and a collector region extending below the shallow trench isolation structure and contacting the extrinsic base region.

13 . The structure of claim 12 , wherein the extrinsic base region is bounded by the shallow trench isolation structure.

14 . The structure of claim 13 , wherein the emitter region is on a first side of the extrinsic base region adjacent to the shallow trench isolation structure and the collector region is on a second side of the extrinsic base region adjacent to the shallow trench isolation structure.

15 . The structure of claim 14 , wherein the emitter region comprises an N+ well implant region extending underneath the shallow trench isolation structure, the extrinsic base region comprises a p-well extending below a surface of the shallow trench isolation structure, and an interface of the N+ well implant region and the p-well comprises a p-n junction under the shallow trench isolation structure.

16 . The structure of claim 15 , wherein the collector region comprises an N+ well implant region and a N− well implant region which extends underneath the shallow trench isolation structure, and the N− well implant region contacts the p-well and comprises a p-n junction region between the collector region and the extrinsic base region.

17 . The structure of claim 12 , wherein the extrinsic base region, the emitter region and the collector region are isolated in the semiconductor substrate material by a deep n-well and deep trench isolation structures contacting the deep n-well.

18 . The structure of claim 12 , wherein the extrinsic base region, the emitter region and the collector region are isolated in the semiconductor substrate material by a deep n-well and n-well regions contacting the deep n-well.

19 . The structure of claim 12 , wherein the extrinsic base region, the emitter region and the collector region comprise epitaxial semiconductor material adjacent to the shallow trench isolation structure, and the epitaxial semiconductor material of the extrinsic base region comprises SiGe.

20 . A method comprising:
forming an extrinsic base region within a semiconductor substrate material; forming a shallow trench isolation structure extending into the semiconductor substrate material and bounding the extrinsic base region; forming an emitter region adjacent to the shallow trench isolation structure and on a side of the extrinsic base region; and forming a collector region adjacent to the shallow trench isolation structure and on an opposing side of the extrinsic base region.

Assignees

• Globalfoundries Us Inc

Inventors

• Singh Jagar
• Wolf Randy L

Classifications

• H10D62/832

  being Group IV materials comprising two or more elements, e.g. SiGe · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D62/114

  PN junction isolations · CPC title

• H10D10/061

  of lateral BJTs  (of heterojunction BJTs H10D10/021; of thin film BJTs H10D10/041) · CPC title

• H10D10/80

  Heterojunction BJTs · CPC title