Semiconductor apparatus and method for manufacturing semiconductor apparatus

Patent metadata

Field	Value
Publication number	US-2023056708-A1
Application number	US-202117797809-A
Country	US
Kind code	A1
Filing date	Feb 15, 2021
Priority date	Feb 13, 2020
Publication date	Feb 23, 2023
Grant date	—

Abstract

Please replace the currently pending Abstract with the following amended A parasitic capacitance of a wiring arranged on a back surface side of a semiconductor substrate is reduced. A semiconductor apparatus includes a semiconductor substrate, a back surface side wiring, a through wiring, and a separation region. In the semiconductor substrate, a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side. The back surface side wiring is arranged on a back surface side of the semiconductor substrate. The through wiring is arranged in a through hole formed in the semiconductor substrate to connect the front surface side wiring and the back surface side wiring. The separation region is arranged between the semiconductor substrate and the back surface side wiring.

First claim

What is claimed is:

1 . A semiconductor apparatus comprising:
a semiconductor substrate in which a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side; a back surface side wiring arranged on a back surface side of the semiconductor substrate; and a separation region arranged between the semiconductor substrate and the back surface side wiring.

2 . The semiconductor apparatus according to claim 1 , further comprising a through wiring arranged in a through hole formed in the semiconductor substrate and connecting the front surface side wiring and the back surface side wiring.

3 . The semiconductor apparatus according to claim 1 , wherein the separation region includes a resin.

4 . The semiconductor apparatus according to claim 3 , wherein the separation region includes a photosensitive resin.

5 . The semiconductor apparatus according to claim 1 , wherein the separation region includes an inorganic material.

6 . The semiconductor apparatus according to claim 1 , wherein the separation region is formed to have a thickness of equal to or greater than 5 μm.

7 . The semiconductor apparatus according to claim 1 , wherein the separation region is arranged in a recess portion formed on a back surface side of the semiconductor substrate.

8 . The semiconductor apparatus according to claim 7 , wherein the separation region includes a gap.

9 . The semiconductor apparatus according to claim 7 , wherein the back surface side wiring is provided so as to at least partially overlap the recess portion in plan view.

10 . The semiconductor apparatus according to claim 7 , wherein a plurality of types of recess portions having different depths is formed as the recess portion.

11 . The semiconductor apparatus according to claim 7 , wherein the recess portion is formed so as to overlap a plurality of the back surface side wiring in plan view.

12 . The semiconductor apparatus according to claim 7 , wherein the recess portion is formed so as to form a polygonal or circular periodic structure in plan view.

13 . The semiconductor apparatus according to claim 7 , further comprising:
a through wiring arranged in a through hole formed in the semiconductor substrate and connecting the front surface side wiring and the back surface side wiring; and a liner film including an insulating material, covering at least a part of the through wiring, and interposed between the through wiring and the separation region.

14 . The semiconductor apparatus according to claim 1 , wherein the separation region includes a gap.

15 . The semiconductor apparatus according to claim 14 , further comprising
a through wiring arranged in a through hole formed in the semiconductor substrate and connecting the front surface side wiring and the back surface side wiring, wherein the separation region includes an in-hole separation region portion covering an inner circumferential surface of the through hole and a back surface side separation region portion formed on a back surface side of the semiconductor substrate, and the gap is formed in the back surface side separation region portion.

16 . The semiconductor apparatus according to claim 2 , wherein the separation region is further arranged between the semiconductor substrate and the through wiring.

17 . The semiconductor apparatus according to claim 2 , wherein the separation region is used as a mask in etching for forming the through hole in the semiconductor substrate.

18 . The semiconductor apparatus according to claim 1 , further comprising an insulating film that insulates the back surface side wiring.

19 . The semiconductor apparatus according to claim 1 , wherein the semiconductor element is a photoelectric conversion element that performs photoelectric conversion of incident light.

20 . A method for manufacturing a semiconductor apparatus, the method comprising:
a separation region arrangement step of arranging a separation region on a back surface side of a semiconductor substrate on which a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side; a through hole forming step of forming a through hole in the semiconductor substrate; a back surface side wiring arrangement step of arranging a back surface side wiring on the back surface side of the semiconductor substrate; and a through wiring arrangement step of arranging a through wiring connecting the front surface side wiring and the back surface side wiring in the through hole that has been formed.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Sasaki Naoto
• Saitou Kenichi
• Hayashi Yusuke
• Yamada Atsuhiko
• Shigetoshi Takushi
• Ooi Takuya

Classifications

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title