Imaging device and electronic device

Patent metadata

Field	Value
Publication number	US-2023054986-A1
Application number	US-202117904400-A
Country	US
Kind code	A1
Filing date	Feb 22, 2021
Priority date	Mar 6, 2020
Publication date	Feb 23, 2023
Grant date	—

Abstract

An imaging device capable of image processing is provided. The imaging device has an image recognition function. In the imaging device, cells have a function of acquiring imaging data and a function of retaining weight data. Among the cells arranged in a matrix, some of the cells acquire imaging data and the rest of the cells retain weight data. Then, arithmetic operation is performed using the imaging data and the weight data. For example, all the imaging data can be subjected to arithmetic operation where products of the imaging data and the weight data are calculated and the sum of the calculated products is calculated. That is, product-sum operation can be performed. When an arithmetic operation result is captured by a neural network such as a convolutional neural network (CNN) or the like, the additional function can be used because image processing can be performed on the imaging data.

First claim

1 . An imaging device comprising:
a cell array where a plurality of cells are arranged in a matrix; and a logic circuit, wherein each of the plurality of cells includes a photoelectric conversion element, wherein a first cell of the plurality of cells is configured to acquire imaging data using the photoelectric conversion element, wherein a second cell of the plurality of cells is configured to retain weight data, and wherein the logic circuit is configured to perform an arithmetic operation using the imaging data acquired by the first cell and the weight data retained by the second cell.

2 . The imaging device according to claim 1 , wherein the logic circuit is configured to calculate a product of the imaging data and the weight data.

3 . An imaging device comprising:
a cell array where a plurality of cells are arranged in a matrix; and a logic circuit, wherein each of the plurality of cells includes a photoelectric conversion element, wherein each of the plurality of cells is configured to acquire imaging data using the photoelectric conversion element, wherein each of the plurality of cells is configured to retain weight data, and wherein the logic circuit is configured to perform an arithmetic operation using first imaging data, second imaging data, first weight data, and second weight data in the case where, among the plurality of cells, a first cell acquires the first imaging data, a second cell acquires the second imaging data, a third cell retains the first weight data, and a fourth cell retains the second weight data.

4 . The imaging device according to claim 3 , wherein the logic circuit is configured to calculate the sum of a product of the first imaging data and the first weight data and a product of the second imaging data and the second weight data.

5 . The imaging device according to claim 1 , further comprising a read circuit,
wherein each of the first cell and the second cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein the one of the source and the drain of the second transistor is electrically connected to a gate of the third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the logic circuit, wherein the other of the source and the drain of the fourth transistor is electrically connected to the read circuit, wherein the second cell is configured to retain the weight data supplied through the source and the drain of the second transistor, wherein the first cell is configured to output the imaging data from the other of the source and the drain of the third transistor or the other of the source and the drain of the fourth transistor, and wherein the second cell is configured to output the weight data from the other of the source and the drain of the third transistor.

6 . The imaging device according to claim 5 ,
wherein the first cell is configured to output the imaging data as binary data from the other of the source and the drain of the third transistor, and wherein the second cell is configured to output the weight data as binary data from the other of the source and the drain of the third transistor.

7 . The imaging device according to claim 5 ,
wherein the first transistor and the second transistor each include a metal oxide in a channel formation region, and wherein the metal oxide contains In, Zn, and M, M being Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf.

8 . The imaging device according to claim 5 , further comprising a coloring layer,
wherein at least one of the first to fourth transistors has a region overlapping the photoelectric conversion element and the coloring layer, and wherein the coloring layer has a function of a microlens.

9 . The imaging device according to claim 8 ,
wherein the logic circuit includes a fifth transistor, and wherein the logic circuit has a region where the fifth transistor, at least one of the first to fourth transistors, the photoelectric conversion element, and the coloring layer overlap each other.

10 . The imaging device according to claim 1 , further comprising a read circuit and an A/D converter circuit, wherein each of the first cell and the second cell includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor, wherein one electrode of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein the one of the source and the drain of the second transistor is electrically connected to a gate of the third transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein the one of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to the read circuit, wherein the one of the source and the drain of the fifth transistor is electrically connected to the A/D converter circuit, wherein the A/D converter circuit is electrically connected to the logic circuit, wherein a first potential is supplied to the other of the source and the drain of the third transistor, wherein a second potential is supplied to the other of the source and the drain of the fifth transistor, wherein the second cell is configured to retain the weight data supplied through the source and the drain of the second transistor, wherein the first cell is configured to output the imaging data from the one of the source and the drain of the third transistor or the other of the source and the drain of the fourth transistor, and wherein the first cell is configured to output the weight data from the one of the source and the drain of the third transistor.

11 . The imaging device according to claim 10 ,
wherein the first transistor and the second transistor each include a metal oxide in a channel formation region, and wherein the metal oxide contains In, Zn, and M, M being Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, or Hf.

12 . The imaging device according to claim 10 , further comprising a coloring layer,
wherein at least one of the first to fifth transistors has a region overlapping the photoelectric conversion element and the coloring layer, and wherein the coloring layer has a function of a microlens.

13 . The imaging device according to claim 12 ,
wherein the logic circuit includes a sixth transistor, and wherein the logic circuit has a region where the sixth transistor, at least one of the first to fifth transistors, the photoelectric conversion element, and the coloring layer overlap each other.

14 . An electronic device comprising:
the imaging device according to claim 1 , and a display portion.

15 . The imaging device according to claim 3 , further comprising a read circuit,
wherein each of the first cell, the secon

Assignees

• Semiconductor Energy Lab

Inventors

• Yoneda Seiichi
• Ikeda Takayuki
• Inoue Hiroki
• Negoro Yusuke
• Yamazaki Shunpei

Classifications

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H10F39/8063

  Microlenses · CPC title

• H10F39/811

  Interconnections · CPC title

• H10D30/67

  Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)} · CPC title

• H10F39/18 Primary

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title