Systems and methods for distributed business process management
US-2019019121-A1 · Jan 17, 2019 · US
Arithmetic processing device and arithmetic processing method
US2023010536A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2023010536-A1 |
| Application number | US-202217729025-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 26, 2022 |
| Priority date | Jul 7, 2021 |
| Publication date | Jan 12, 2023 |
| Grant date | — |
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- Title
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Abstract
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An arithmetic processing device includes: a memory; and a processor coupled to the memory and configured to: execute a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings; measure a processing time of each of the plurality of pipeline stages; and set a priority of the plurality of pipeline stages in a descending order of the measured processing time.
First claim
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What is claimed is: 1 . An arithmetic processing device comprising: a memory; and a processor coupled to the memory and configured to: execute a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings; measure a processing time of each of the plurality of pipeline stages; and set a priority of the plurality of pipeline stages in a descending order of the measured processing time. 2 . The arithmetic processing device according to claim 1 , wherein the processor changes the priority for each of the plurality of pipeline stages by hooking an application programmable interface of a driver that controls an operation of the processor. 3 . The arithmetic processing device according to claim 1 , wherein a measurement of the processing time and a setting of the priority are performed before an execution of the plurality of data processes. 4 . An arithmetic processing method comprising: executing, by a processor, a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings; measuring a processing time of each of the plurality of pipeline stages; and setting a priority of the plurality of pipeline stages in a descending order of the measured processing time. 5 . The arithmetic processing method according to claim 4 , further comprising: changing the priority for each of the plurality of pipeline stages by hooking an application programmable interface of a driver that controls an operation of the processor. 6 . The arithmetic processing method according to claim 4 , wherein a measurement of the processing time and a setting of the priority are performed before an execution of the plurality of data processes.
Assignees
Inventors
Classifications
- G06F9/3001Primary
Arithmetic instructions · CPC title
Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage · CPC title
Configuring for operating with peripheral devices; Loading of device drivers · CPC title
- G06F9/3869Primary
Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking · CPC title
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- What does patent US2023010536A1 cover?
- An arithmetic processing device includes: a memory; and a processor coupled to the memory and configured to: execute a plurality of data processes each of which is divided into a plurality of pipeline stages in parallel at different timings; measure a processing time of each of the plurality of pipeline stages; and set a priority of the plurality of pipeline stages in a descending order of the …
- Who is the assignee on this patent?
- Fujitsu Ltd
- What technology area does this patent fall under?
- Primary CPC classification G06F9/3001. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Jan 12 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).