Control system with cascade driving circuits and related driving method

Patent metadata

Field	Value
Publication number	US-2023005451-A1
Application number	US-202217945082-A
Country	US
Kind code	A1
Filing date	Sep 14, 2022
Priority date	Aug 6, 2020
Publication date	Jan 5, 2023
Grant date	—

Abstract

A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.

First claim

What is claimed is:

1 . A control system, comprising:
a plurality of driving circuits coupled in series, comprising:
a first driving circuit, comprising:
a first receiver;
a first transmitter, coupled to the first receiver; and
a first flag signal selector, coupled between the first receiver and the first transmitter; and

a second driving circuit, coupled to the first driving circuit, comprising:
a second receiver;
a second transmitter, coupled to the second receiver; and
a second flag signal selector, coupled between the second receiver and the second transmitter.

2 . The control system of claim 1 , further comprising:
a controller, coupled to the first driving circuit and the second driving circuit, configured to receive a first driving signal from the first driving circuit and receive a second driving signal from the second driving circuit.

3 . The control system of claim 1 , wherein each of the first flag signal selector and the second flag signal selector comprises:
a select circuit, comprising a plurality of input terminals, an output terminal and a select terminal; and a plurality of flip-flops, each coupled to one of the plurality of input terminals of the select circuit.

4 . The control system of claim 3 , wherein each of the plurality of flip-flops are connected in series.

5 . The control system of claim 3 , wherein the select circuit is configured to selectively output a flag signal from one of the plurality of flip-flops, to synchronize a first driving signal output by the first driving circuit with a second driving signal output by the second driving circuit.

6 . The control system of claim 3 , wherein the plurality of flip-flops are configured to receive a plurality of clock signals having different phases, respectively.

7 . A driving circuit, comprising:
a receiver; a transmitter, coupled to the receiver; and a flag signal selector, coupled between the receiver and the transmitter; wherein the flag signal selector comprises a select circuit coupled to output terminals of a plurality of flip-flops.

8 . The driving circuit of claim 7 , wherein each of the plurality of flip-flops are connected in series.

9 . The driving circuit of claim 7 , wherein the select circuit is configured to selectively output a flag signal from one of the plurality of flip-flops, to synchronize output timing of a driving signal output by the driving circuit.

10 . The driving circuit of claim 7 , wherein the plurality of flip-flops are configured to receive a plurality of clock signals having different phases, respectively.

11 . A method of driving a controller for a control system having a plurality of driving circuits coupled in series, the plurality of driving circuits comprising a first driving circuit and a second driving circuit, the method comprising:
receiving, by the first driving circuit, a first signal from a previous stage; transmitting, by the first driving circuit, the first signal to the second driving circuit; delaying the first signal to generate a second signal according to a flag signal by performing at least one of the following steps:
selecting a first flag signal from a plurality of first flag signals corresponding to different clock cycles in each of the first driving circuit and the second driving circuit; and
selecting a second flag signal from a plurality of second flag signals corresponding to different phases in each of the first driving circuit and the second driving circuit; and
controlling a timing of outputting the second signal to the controller by using the selected flag signal, to synchronize the second signal output by the first driving circuit and the second driving circuit.

12 . The method of claim 11 , wherein the step of selecting the first flag signal is implemented in a coarse delay circuit for providing coarse delay adjustment on the first signal, and the step of selecting the second flag signal is implemented in a fine delay circuit for providing fine delay adjustment on the first signal.

13 . The method of claim 12 , wherein the coarse delay circuit is configured to synchronize the second signal of the first driving circuit and the second driving circuit by selecting different first flag signals corresponding to different clock cycles for the first driving circuit and the second driving circuit.

14 . The method of claim 12 , wherein the fine delay circuit is configured to synchronize the second signal of the first driving circuit and the second driving circuit by selecting different second flag signals corresponding to different clock phases for the first driving circuit and the second driving circuit.

Assignees

• Novatek Microelectronics Corp

Inventors

• Yeh Che-Wei
• Liang Keko-Chun
• Wang Yu-Hsiang
• Fang Yong-Ren
• Liu Yi-Chuan
• Tsai Yi-Yang
• Fang Po-Hsiang

Classifications

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G5/12 Primary

  Synchronisation between the display unit and other units, e.g. other display units, video-disc players · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G09G2352/00

  Parallel handling of streams of display data · CPC title