Display apparatus

Patent metadata

Field	Value
Publication number	US-2022415987-A1
Application number	US-202217725447-A
Country	US
Kind code	A1
Filing date	Apr 20, 2022
Priority date	Jun 24, 2021
Publication date	Dec 29, 2022
Grant date	—

Abstract

A display apparatus includes a substrate including a subpixel area, a pixel circuit layer arranged over the substrate and defining a pixel circuit overlapping the subpixel area, and a display element layer arranged over the pixel circuit layer and including a display element electrically connected to the pixel circuit, wherein the pixel circuit layer includes a lower inorganic insulating layer arranged over the substrate, a plurality of inorganic insulating patterns overlapping the subpixel area, arranged over the lower inorganic insulating layer, and spaced apart from each other in a plan view, and an organic insulating layer covering the plurality of inorganic insulating patterns.

First claim

What is claimed is:

1 . A display apparatus comprising:
a substrate including a subpixel area; a pixel circuit layer arranged over the substrate and defining a pixel circuit overlapping the subpixel area; and a display element layer arranged over the pixel circuit layer and including a display element electrically connected to the pixel circuit, wherein the pixel circuit layer includes: a lower inorganic insulating layer arranged over the substrate; a plurality of inorganic insulating patterns overlapping the subpixel area, arranged over the lower inorganic insulating layer, and spaced apart from each other in a plan view; and an organic insulating layer covering the plurality of inorganic insulating patterns.

2 . The display apparatus of claim 1 , wherein a portion of the organic insulating layer is arranged inside a space defined between the plurality of inorganic insulating patterns adjacent to each other.

3 . The display apparatus of claim 2 , wherein the space overlaps the display element.

4 . The display apparatus of claim 1 , wherein the pixel circuit layer further includes:
a first conductive line arranged between one of the plurality of inorganic insulating patterns and the substrate and extending in a first direction; and a second conductive line arranged between another one of the plurality of inorganic insulating patterns and the substrate and extending in the first direction.

5 . The display apparatus of claim 4 , wherein the pixel circuit layer further includes a third conductive line arranged between the organic insulating layer and the display element layer, overlapping the subpixel area, and extending in a second direction intersecting with the first direction.

6 . The display apparatus of claim 1 , wherein the lower inorganic insulating layer includes a first gate insulating layer and a second gate insulating layer sequentially arranged over the substrate, and
the pixel circuit layer further includes: a semiconductor layer arranged between the substrate and the first gate insulating layer; a first gate conductive layer arranged between the first gate insulating layer and the second gate insulating layer; and a plurality of conductive patterns arranged between the plurality of inorganic insulating patterns and the organic insulating layer.

7 . The display apparatus of claim 6 , wherein each of the plurality of conductive patterns is arranged over corresponding one of the plurality of inorganic insulating patterns.

8 . The display apparatus of claim 6 , wherein at least two of the plurality of conductive patterns are arranged over one of the plurality of inorganic insulating patterns.

9 . The display apparatus of claim 1 , wherein the lower inorganic insulating layer includes a first gate insulating layer, a second gate insulating layer, a lower insulating layer, and a third gate insulating layer sequentially arranged over the substrate, and
the pixel circuit layer further includes: a first semiconductor layer arranged between the substrate and the first gate insulating layer and including a silicon semiconductor; a second semiconductor layer arranged between the lower insulating layer and the third gate insulating layer and including an oxide semiconductor; and a plurality of conductive patterns arranged between the plurality of inorganic insulating patterns and the organic insulating layer.

10 . The display apparatus of claim 1 , wherein the subpixel area includes a first subpixel area, a second subpixel area, and a third subpixel area,
the plurality of inorganic insulating patterns are arranged in the first subpixel area, the lower inorganic insulating layer includes a first lower inorganic insulating pattern overlapping the second subpixel area and a second lower inorganic insulating pattern overlapping the third subpixel area and spaced apart from the first lower inorganic insulating pattern in the plan view, and the pixel circuit layer further includes a first upper inorganic insulating pattern arranged over the first lower inorganic insulating pattern and a second upper inorganic insulating pattern arranged over the second lower inorganic insulating pattern and spaced apart from the first upper inorganic insulating pattern in the plan view.

11 . A display apparatus comprising:
a substrate including a subpixel area; a pixel circuit layer arranged over the substrate and defining a pixel circuit overlapping the subpixel area; and a display element layer arranged over the pixel circuit layer and including a display element electrically connected to the pixel circuit, wherein the pixel circuit layer includes: a first conductive line and a second conductive line overlapping the subpixel area and extending in a first direction; a plurality of inorganic insulating patterns arranged over the first conductive line and the second conductive line and spaced apart from each other in a plan view; an organic insulating layer covering the plurality of inorganic insulating patterns; and a third conductive line arranged over the organic insulating layer and extending in a direction intersecting with the first direction.

12 . The display apparatus of claim 11 , wherein a portion of the organic insulating layer is arranged inside a space defined between the plurality of inorganic insulating patterns adjacent to each other.

13 . The display apparatus of claim 12 , wherein the space overlaps the display element.

14 . The display apparatus of claim 11 , wherein the first conductive line overlaps one of the plurality of inorganic insulating patterns, and the second conductive line overlaps another one of the plurality of inorganic insulating patterns.

15 . The display apparatus of claim 11 , wherein the first conductive line is a scan line configured to transmit a scan signal, and wherein
the second conductive line is an emission control line configured to transmit an emission control signal.

16 . The display apparatus of claim 11 , wherein the pixel circuit layer further includes a lower inorganic insulating layer arranged between the substrate and the plurality of inorganic insulating patterns and including a first gate insulating layer and a second gate insulating layer that are sequentially stacked.

17 . The display apparatus of claim 16 , wherein the pixel circuit layer further includes:
a semiconductor layer arranged between the substrate and the first gate insulating layer; a first gate conductive layer arranged between the first gate insulating layer and the second gate insulating layer; and a plurality of conductive patterns arranged between the plurality of inorganic insulating patterns and the organic insulating layer.

18 . The display apparatus of claim 17 , wherein at least two of the plurality of conductive patterns are arranged over one of the plurality of inorganic insulating patterns.

19 . The display apparatus of claim 11 , wherein the pixel circuit layer further includes:
a lower inorganic insulating layer arranged between the substrate and the plurality of inorganic insulating patterns and including a first gate insulating layer, a second gate insulating layer, a lower insulating layer, and a third gate insulating layer that are sequentially stacked; a first semiconductor layer arranged between the substrate and the first gate insulating layer and including a silicon semiconductor; a second semiconductor layer arranged between the lower insulating layer and the third gate insulating layer and including an oxide semiconductor; and a

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Jonghyun
• Ju Jinho
• Kim Younjoon

Classifications

• H01L27/3265

  Electricity · mapped topic

• H01L27/3262 Primary

  Electricity · mapped topic

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

• H10K59/124 Primary

  Insulating layers formed between TFT elements and OLED elements · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title