Secure direct peer-to-peer memory access requests between devices

Patent metadata

Field	Value
Publication number	US-2022405212-A1
Application number	US-202117352631-A
Country	US
Kind code	A1
Filing date	Jun 21, 2021
Priority date	Jun 21, 2021
Publication date	Dec 22, 2022
Grant date	—

Abstract

An embodiment of an integrated circuit comprises circuitry to store memory protection information for a non-host memory in a memory protection cache, and perform one or more memory protection checks on a translated access request for the non-host memory based on the stored memory protection information. Other embodiments are disclosed and claimed.

First claim

What is claimed is:

1 . An apparatus, comprising:
a memory protection cache to store memory protection information for a non-host memory; and circuitry coupled to the memory protection cache to perform one or more memory protection checks on a translated access request for the non-host memory based on the stored memory protection information.

2 . The apparatus of claim 1 , wherein the circuitry is further to:
synchronize the stored memory protection information with a memory protection unit of a host.

3 . The apparatus of claim 2 , wherein the circuitry is further to:
provide secure direct peer-to-peer memory access to the non-host memory without intervention by the host.

4 . The apparatus of claim 3 , wherein the circuitry is further to:
block or allow a direct peer-to-peer memory access request for the non-host memory based on the memory protection information stored in the memory protection cache.

5 . The apparatus of claim 2 , wherein the circuitry is further to:
determine if the translated access request comes from the host; and, if so determined, bypass the one or more memory protection checks on the translated access request.

6 . The apparatus of claim 2 , wherein the circuitry is further to:
determine if the translated access request misses the memory protection cache based on information received in the translated access request; and, if so determined, request the memory protection unit of the host to fill in memory protection information for the translated access request.

7 . The apparatus of claim 6 , wherein the circuitry is further to:
notify a requestor to retry the translated access request that misses the memory protection cache, along with hold-off information.

8 . An integrated circuit comprising circuitry to:
store memory protection information for a host memory in an input/output memory protection unit (IO-MPU); and synchronize the stored memory protection information with a memory protection cache (MPC) of a device communicatively coupled to the host.

9 . The integrated circuit of claim 8 , wherein the circuitry is further to:
receive a MPC fill request at the IO-MPU from the device.

10 . The integrated circuit of claim 9 , wherein the circuitry is further to:
perform a host-permission table walk and validate access permissions at the IO-MPU in response to the MPC fill request; and return information from the IO-MPU to the device in a form of a MPC fill response.

11 . The integrated circuit of claim 8 , wherein the circuitry is further to:
receive a request at the IO-MPU from system software to invalidate MPC information.

12 . The integrated circuit of claim 11 , wherein the circuitry is further to:
generate a MPC invalidation request to the device in response to the request; and receive a MPC invalidation response from the device.

13 . The integrated circuit of claim 12 , wherein the circuitry is further to:
one or more of update tracking information and notify the system software about the MPC invalidation response.

14 . The integrated circuit of claim 8 , wherein the host memory comprises system memory.

15 . A method, comprising:
storing memory protection information for a non-host memory in a memory protection cache; and performing one or more memory protection checks on a translated access request for the non-host memory based on the stored memory protection information.

16 . The method of claim 15 , further comprising:
synchronizing the stored memory protection information with a memory protection unit of a host.

17 . The method of claim 16 , further comprising:
providing secure direct peer-to-peer memory access to the non-host memory without intervention by the host.

18 . The method of claim 16 , further comprising:
bypassing a root port of the host for the translated access request for the non-host memory.

19 . The method of claim 16 , further comprising:
determining if the translated access request comes from the host; and, if so determined, bypassing the one or more memory protection checks on the translated access request.

20 . The method of claim 16 , further comprising:
determining if the translated access request misses the memory protection cache based on information received in the translated access request; and, if so determined, requesting the memory protection unit of the host to fill in memory protection information for the translated access request.

21 . The method of claim 20 , further comprising:
notifying a requestor to retry the translated access request that misses the memory protection cache, along with hold-off information.

Assignees

• Intel Corp

Inventors

• Kakaiya Utkarsh Y
• Sankaran Rajesh
• Koufaty David

Classifications

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F12/1425

  the protection being physical, e.g. cell, word, block · CPC title

• G06F12/1458 Primary

  by checking the subject access rights · CPC title

• G06F12/145

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title