Intelligent cache with read destructive memory cells

Patent metadata

Field	Value
Publication number	US-2022405208-A1
Application number	US-202217844141-A
Country	US
Kind code	A1
Filing date	Jun 20, 2022
Priority date	Jun 18, 2021
Publication date	Dec 22, 2022
Grant date	—

Abstract

A data storage system can employ a read destructive memory configured to fill a first cache with a first data set from a data repository prior to populating a second cache with a second data set describing the first data set with the first and second cache each having non-volatile ferroelectric memory cells. An entirety of the first cache may be read in response to a cache hit in the second cache with the cache hit responsive to a data read command from a host and with the first cache being read without a refresh operation restoring the data of the first cache.

First claim

What is claimed is:

1 . An apparatus comprising:
a cache consisting of read destructive memory cells; a map connected to the first cache, the map consisting of read destructive memory cells storing information about data resident in the first cache; and a controller connected to the first cache and map, the controller configured to output less than an entirety of the data stored in the first cache in response to a map hit by a host data request, the entirety of the first cache and map subsequently filled with different data identified by the controller.

2 . The apparatus of claim 1 , wherein the read destructive memory cells of the cache are arranged in a two dimensional array.

3 . The apparatus of claim 1 , wherein the read destructive memory cells of the cache are arranged in a three dimensional array.

4 . The apparatus of claim 1 , wherein a read buffer is connected to the cache, the read buffer consisting of non-read destructive solid-state memory cells.

5 . The apparatus of claim 1 , wherein a data repository is connected to the cache, the data repository consisting of non-read destructive solid-state memory cells.

6 . The apparatus of claim 1 , further comprising a second cache connected to the map and first cache, the second cache consisting of read destructive memory cells, data stored in the second cache described by the map.

7 . The apparatus of claim 6 , wherein the second cache has a different capacity than the first cache.

8 . The apparatus of claim 1 , wherein the read destructive memory cells are non-volatile ferroelectric solid-state cells.

9 . A method comprising:
filling a cache with a first data set from a data repository; populating a cache map with a second data set describing the first data set, the cache and cache map each comprising read destructive memory cells; reading an entirety of the cache in response to a cache hit to the cache map by a host request, the cache read without a refresh operation restoring the data of the cache, and filling the cache with data predicted by a controller to be requested by a host in the future.

10 . The method of claim 9 , wherein the controller maintains a list of data to speculatively fill the cache in response to satisfaction of the host request.

11 . The method of claim 10 , wherein the list of data is populated based on frequency of data accesses over time.

12 . The method of claim 10 , wherein the list of data is populated based on a source of data.

13 . The method of claim 10 , wherein the list of data is populated based on a timestamp of when data is written to the data repository.

14 . The method of claim 10 , wherein the list of data is populated based on size.

15 . The method of claim 9 , wherein the cache map is rewritten in response to cache miss by a data request from a host.

16 . The method of claim 9 , wherein the data predicted by the controller fills the cache without an existing request from a host.

17 . A method comprising:
filling a cache with a first data set from a data repository; populating a cache map with a second data set describing the first data set, the cache and cache map each comprising read destructive memory cells; reading an entirety of the cache in response to a cache hit to the cache map by a host request, the cache read without a refresh operation restoring the data of the cache, filling the cache with data identified by a controller as compromised; and applying an error correction code to the data identified as compromised while the data is resident in the cache.

18 . The method of claim 17 , wherein a memory stores multiple different versions of error correction code for selection by the controller.

19 . The method of claim 18 , wherein the controller selects a version of error correction based on availability of processing resources.

20 . The method of claim 17 , wherein the compromised data has experienced an error and cannot be accurately read by the controller.

Assignees

• Seagate Technology Llc

Inventors

• Trantham Jon D
• Viraraghavan Praveen
• Dykes John W
• Gilbert Ian J
• Kalarickal Sangita Shreedharan
• Totin Matthew J
• El-Batal Mohamad
• Mehta Darshana H

Classifications

• G06F12/0891 Primary

  using clearing, invalidating or resetting means · CPC title

• G06F2212/60

  Details of cache memory · CPC title

• G11C15/046

  using non-volatile storage elements · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0871 Primary

  Allocation or management of cache space · CPC title