Enhanced gain of operational amplifiers through low-frequency zero positioning

Patent metadata

Field	Value
Publication number	US-2022399863-A1
Application number	US-202217749434-A
Country	US
Kind code	A1
Filing date	May 20, 2022
Priority date	May 20, 2021
Publication date	Dec 15, 2022
Grant date	—

Abstract

An amplifier circuit comprises a multi-stage amplifier having a plurality of amplifiers cascaded between an input port Vin and an output port Vout to form a differential input stage and N subsequent gain stages, a capacitive load CL coupled to the output port Vout, and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ωt of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ωt.

First claim

1 . An amplifier circuit comprising:
a multi-stage amplifier having a plurality of amplifiers cascaded between an input port V in and an output port V out to form a differential input stage and N subsequent gain stages; a capacitive load C L coupled to the output port V out ; and a compensation network coupled to the multi-stage amplifier and configured for positioning Pole-Zero pairs of each stage of the multi-stage amplifier below a unity gain frequency ω t of the multi-stage amplifier when compensated, with Zeros positioned lower than Poles so as to increase the unity gain frequency ω t .

2 . The amplifier circuit of claim 1 , wherein the compensation network is further configured for positioning the Pole-Zero pairs of each stage of the multi-stage amplifier above a 3 dB frequency ω P0 of the multi-stage amplifier when compensated so as to increase a load-drive capability of the multi-stage amplifier.

3 . The amplifier circuit of claim 2 , wherein the capacitive load C L is in a range of pF to μF.

4 . The amplifier circuit of claim 3 , wherein the capacitive load C L is in a nF range.

5 . The amplifier circuit of claim 1 , wherein the multi-stage amplifier is a Miller RC differential-ended two-stage operational transconductance amplifier.

6 . The amplifier circuit of claim 1 , wherein N is an integer from 2 to 8.

7 . The amplifier circuit of claim 1 , wherein each of the N subsequent gain stages is a replicated common source gain stage.

8 . The amplifier circuit of claim 1 , wherein each of the N subsequent gain stages produces a same direct current (DC) gain as remaining ones of the N subsequent gain stages.

9 . The amplifier circuit of claim 8 , wherein each common source gain stage has a DC gain between about 20 dB and about 25 dB.

10 . The amplifier circuit of claim 1 , wherein the compensation network comprises a plurality of compensation circuits, with a compensation circuit being provided for each stage of the multi-stage amplifier, and further wherein values of the compensation circuit for a 2-stage amplifier are scaled to size the compensation circuit of higher stages.

11 . The amplifier circuit of claim 10 , wherein the compensation circuit for each stage of the multi-stage amplifier is a multi-Miller RC compensation circuit, the plurality of compensation circuits configured to create paths between inputs and outputs of all stages of the multi-stage amplifier.

12 . The amplifier circuit of claim 11 , wherein the multi-stage amplifier comprises a plurality of compensation resistors and a plurality of compensation capacitors, further wherein, when a new stage is added to the multi-stage amplifier, a size of the compensation resistors of preceding stages of the multi-stage amplifier is reduced to increase a frequency of Zeros of the new stage and a size of the compensation capacitors of the preceding stages is increased to decrease a frequency of Poles of the new stage.

13 . The amplifier circuit of claim 12 , wherein each stage higher than the second stage comprises a compensation capacitor sized to a minimum capacitance value identified for the 2-stage amplifier.

14 . The amplifier circuit of claim 1 , wherein the multi-stage amplifier comprises at least one common-mode feedback circuit configured to apply biasing voltages to outputs of the stages of the multi-stage amplifier.

15 . The amplifier circuit of claim 14 , wherein, for N≤3, the at least one common-mode feedback circuit comprises a first common-mode feedback circuit connected to an output of the second stage of the multi-stage amplifier.

16 . The amplifier circuit of claim 15 , wherein, for N=2, the first common-mode feedback circuit is connected to an output of a second stage of the multi-stage amplifier.

17 . The amplifier circuit of claim 15 , wherein, for N=3, the first common-mode feedback circuit is connected to an output of a third stage of the multi-stage amplifier.

18 . The amplifier circuit of claim 15 , wherein, for N≥4, the at least one common-mode feedback circuit further comprises a second common-mode feedback circuit, the first common-mode feedback circuit connected to an output of a third stage of the multi-stage amplifier and the second common-mode feedback circuit connected to an output of each additional stage following the third stage.

Assignees

• The Royal Institution For The Advancement Of Learning/Mcgill Univ

Inventors

• Mohammed Mahmood A
• Roberts Gordon

Classifications

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F1/083

  in transistor amplifiers (H03F1/10 - H03F1/22 take precedence) · CPC title

• H03F2200/297

  the loading circuit of an amplifying stage comprising a capacitor · CPC title

• H03F2203/45631

  the LC comprising one or more capacitors, e.g. coupling capacitors · CPC title

• H03F2203/45652

  the LC comprising one or more further dif amp stages, either identical to the dif amp or not, in cascade · CPC title