Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022399438-A1
Application number	US-202217830143-A
Country	US
Kind code	A1
Filing date	Jun 1, 2022
Priority date	Jun 15, 2021
Publication date	Dec 15, 2022
Grant date	—

Abstract

P-type low-concentration regions face bottoms of trenches and extend in a longitudinal direction (first direction) of the trenches. The p-type low-concentration regions are adjacent to one another in a latitudinal direction (second direction) of the trenches and connected at predetermined locations by p-type low-concentration connecting portions that are scattered along the first direction and separated from one another by an interval of at least 3 μm. The p-type low-concentration regions and the p-type low-concentration connecting portions have an impurity concentration in a range of 3×1017/cm3 to 9×1017/cm3. A depth from the bottoms of the trenches to lower surfaces of the p-type low-concentration regions is in a range of 0.7 μm to 1.1 μm. Between the bottom of each of the trenches and a respective one of the p-type low-concentration regions, a p+-type high-concentration region is provided. Each p+-type high-concentration region has an impurity concentration that is at least 2 times the impurity concentration of the p-type low-concentration regions.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor substrate containing a semiconductor having band gap that is wider than a band gap of silicon, the semiconductor substrate having a first main surface and a second main surface that are opposite to each other; a first semiconductor region of a first conductivity type, provided in the semiconductor substrate; a second semiconductor region of a second conductivity type, provided between the first main surface of the semiconductor substrate and the first semiconductor region; a plurality of third semiconductor regions of the first conductivity type, selectively provided between the first main surface of the semiconductor substrate and the second semiconductor region; a plurality of trenches penetrating through, in a depth direction of the semiconductor device, the third semiconductor regions and the second semiconductor region and reaching the first semiconductor region, the trenches being provided in a striped pattern extending in a first direction that is parallel to the first main surface of the semiconductor substrate; a plurality of gate electrodes provided in the trenches via a gate insulating film; a first electrode electrically connected to the second semiconductor region and the third semiconductor regions; a second electrode provided on the second main surface of the semiconductor substrate; a plurality of first low-concentration regions of the second conductivity type, selectively provided in the first semiconductor region, each of the first low-concentration regions facing a respective one of bottoms of the trenches; and a plurality of first connecting portions of the second conductivity type, each of the first connecting portions connecting an adjacent two of the first low-concentration regions in a second direction that is parallel to the first main surface of the semiconductor substrate and orthogonal to the first direction, wherein the first low-concentration regions and the first connecting portions are electrically connected to the second semiconductor region, and the first low-concentration regions extend linearly in the first direction, the first low-concentration regions forming a grid-like pattern with the first connecting portions in a plan view of the semiconductor device.

2 . The semiconductor device according to claim 1 , wherein
each of the first low-concentration regions has a first end facing a respective one of the trenches and a second end facing the second electrode, and a distance from the respective trench to the second end is in a range of 0.7 μm to 1.1 μm.

3 . The semiconductor device according to claim 1 , further comprising
a plurality of first high-concentration regions of the second conductivity type, each of the first high-concentration regions electrically connecting a respective one of the first low-concentration regions to the second semiconductor region and having an impurity concentration that is higher than an impurity concentration of the second semiconductor region.

4 . The semiconductor device according to claim 3 , wherein
the first low-concentration regions and the first connecting portions each have an impurity concentration in a range of 3×10 17 /cm 3 to 9×10 17 /cm 3 .

5 . The semiconductor device according to claim 3 , wherein
an interval between an adjacent two of the first connecting portions in the first direction is 3 μm or less.

6 . The semiconductor device according to claim 3 , wherein
each of the first connecting portions has a width in the first direction in a range of 0.5 μm to 1.0 μm.

7 . The semiconductor device according to claim 3 , further comprising
a plurality of second high-concentration regions of the second conductivity type, provided between the bottoms of the trenches and the first low-concentration regions facing the bottoms, respectively, each of the second high-concentration regions being in contact with a respective one of the first low-concentration regions and having an impurity concentration that is higher than the impurity concentrations of the first low-concentration regions and the second semiconductor region.

8 . The semiconductor device according to claim 7 , wherein
the impurity concentration of the second high-concentration regions is at least two times the impurity concentration of the first low-concentration regions.

9 . The semiconductor device according to claim 7 , wherein
the second high-concentration regions are in direct contact with the gate insulating film at the bottoms of the trenches, and each of the second high-concentration regions has an end facing the second electrode and a distance between the end and a bottom of a respective one of the trenches is in a range of 0.1 μm to 0.15 μm.

10 . The semiconductor device according to claim 3 , wherein
the first high-concentration regions are provided in the first semiconductor region, separate from the first low-concentration regions and the trenches, extending in a striped pattern in the first direction, each of the first high-concentration regions being provided between a respective adjacent two of the trenches.

11 . The semiconductor device according to claim 10 , wherein
the first low-concentration regions are electrically connected to the first high-concentration regions via the first connecting portions.

12 . The semiconductor device according to claim 3 , wherein
the first high-concentration regions are provided at intervals in only one sidewall of each of the trenches along the first direction.

13 . The semiconductor device according to claim 12 , wherein
each of the intervals of the first high-concentration regions along the first direction is wider than an interval between the first connecting portions in the first direction.

14 . The semiconductor device according to claim 1 , further comprising
a plurality of second low-concentration regions of the second conductivity type, provided in the first semiconductor region, in contact with the second semiconductor region and the first connecting portions but apart from the first low-concentration regions and the trenches, the second low-concentration regions extending in a striped pattern in the first direction, each of the second low-concentration regions being between a respective adjacent two of the trenches, wherein each of the first low-concentration regions has an end that faces the second electrode, each of the second low-concentration regions has an end that faces the second electrode and that is closer to the first electrode than is the end of the each of the first low-concentration regions, and a distance between the end of the each of the second low-concentration regions and the end of the each of the first low-concentration regions is at least 0.1 μm, and the second low-concentration regions have an impurity concentration that is at least 10 times higher than the impurity concentration of the first low-concentration regions.

15 . The semiconductor device according to claim 1 , wherein
each of the first low-concentration regions has a width that is wider than a width of each of the trenches and that is at least 1.0 μm.

16 . The semiconductor device according to claim 14 , wherein
the impurity concentration of the first low-concentration regions is in a range of 1×10 16 /cm 3 to 8×10 16 /cm 3 .

17 . The semiconductor device according to claim 14 , wherein
the first connecting portions have an impurity concentration that is at least 10 times higher than the impurity concentration of the first low-concentration r

Assignees

• Fuji Electric Co Ltd

Inventors

• Hoshi Yasuyuki

Classifications

• H10P30/22

  using masks · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10W10/01

  Manufacture or treatment · CPC title

• H10W10/00

  Isolation regions in semiconductor bodies between components of integrated devices · CPC title