Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2022392531-A1
Application number	US-202217575724-A
Country	US
Kind code	A1
Filing date	Jan 14, 2022
Priority date	Jun 2, 2021
Publication date	Dec 8, 2022
Grant date	—

Abstract

According to an embodiment, a semiconductor memory device includes a memory cell, a first word line coupled between a control end of the memory cell and a first node, a resistance element coupled between the first node and a second node, a control circuit configured to output a voltage to the second node, a first switch coupled between the first node and a third node, a second switch coupled between the second node and the third node, and a comparator including an input end that receives a signal corresponding to a voltage of the third node.

First claim

1 . A semiconductor memory device, comprising:
a memory cell; a first word line coupled between a control end of the memory cell and a first node; a resistance element coupled between the first node and a second node; a control circuit configured to output a voltage to the second node; a first switch coupled between the first node and a third node; a second switch coupled between the second node and the third node; and a comparator including an input end that receives a signal corresponding to a voltage of the third node.

2 . The device according to claim 1 , further comprising:
a first capacitance element including a first electrode coupled to the third node and a second electrode coupled to a fourth node, wherein the input end of the comparator receives a signal corresponding to the voltage of the third node via the fourth node.

3 . The device according to claim 2 , further comprising:
an amplification circuit including an input end coupled to the fourth node and an output end coupled to a fifth node; and a second capacitance element including a third electrode coupled to the fifth node and a fourth electrode coupled to a sixth node, wherein the input end of the comparator is coupled to the sixth node, and receives the signal corresponding to the voltage of the third node via the sixth node and the fifth node.

4 . The device according to claim 3 , further comprising:
a third switch coupled between the fourth node and a first reference potential node; and a fourth switch coupled between the sixth node and a second reference potential node.

5 . The device according to claim 1 , wherein
the control circuit is further configured to transmit a first signal to a control end of the first switch and transmit a second signal to a control end of the second switch, a level of a voltage of a signal output from the comparator changes in accordance with switching of a voltage of the first signal from a first level to a third level and switching of a voltage of the second signal from a second level to a fourth level subsequent to a period during which the voltage of the first signal is at the first level and the voltage of the second signal is at the second level, the second level being lower than the fourth level if the first level is higher than the third level, and the second level being higher than the fourth level if the first level is lower than the third level.

6 . The device according to claim 5 , wherein
the control circuit is further configured to start outputting a first voltage to the second node in a verify operation on the memory cell, and the change of the signal output from the comparator occurs during the output of the first voltage.

7 . The device according to claim 1 , wherein
the control circuit is further configured to start outputting a first voltage to the first word line via the second node in a verify operation on the memory cell, the control circuit is further configured to transmit a first signal to a control end of the first switch and transmit a second signal to a control end of the second switch, a period during which the first voltage is output to the first word line includes a first period during which a voltage of the first signal is at a first level and a voltage of the second signal is at a second level, and a second period during which the voltage of the first signal is at a third level and the voltage of the second signal is at a fourth level, the first level being higher than the third level, and the second level being lower than the fourth level.

8 . The device according to claim 7 , further comprising:
a source line coupled to the memory cell and a second word line which is a word line adjacent to the first word line, wherein the control circuit is further configured to output a second voltage higher than the first voltage to the second word line and output a third voltage lower than the first voltage to the source line, and the first period and the second period are included in a period during which the second voltage is output to the second word line and the third voltage is output to the source line.

9 . The device according to claim 1 , wherein
the control circuit is further configured to start outputting a first voltage to the first word line via the second node in a verify operation on the memory cell, the control circuit is further configured to transmit a first signal to a control end of the first switch and transmit a second signal to a control end of the second switch, a period during which the first voltage is output to the first word line includes: a first period during which a voltage of the first signal is at a first level and a voltage of the second signal is at a second level; a second period which is after the first period and in which the voltage of the first signal is at a third level and the voltage of the second signal is at a fourth level; and a third period which is after the second period and in which the voltage of the first signal is at the first level and the voltage of the second signal is at the second level, the second level being lower than the fourth level if the first level is higher than the third level, and the second level being higher than the fourth level if the first level is lower than the third level.

10 . The device according to claim 9 , further comprising:
a source line coupled to the memory cell and a second word line which is a word line adjacent to the first word line, wherein the control circuit is further configured to output a second voltage higher than the first voltage to the second word line and output a third voltage lower than the first voltage to the source line, and the first period, the second period, and the third period are included in a period during which the second voltage is output to the second word line and the third voltage is output to the source line.

11 . The device according to claim 1 , wherein
the control circuit is further configured to:
start outputting a first voltage to the first word line via the second node in a first: verify operation on the memory cell to apply a lowest verify voltage to the memory cell; and
start outputting a second voltage to the first word line via the second node in a second verify operation on the memory cell to apply a highest verify voltage to the memory cell,
the control circuit is further configured to transmit a first signal to a control end of the first switch and transmit a second signal to a control end of the second switch, a period during which the first voltage is output to the first word line includes a first period during which a voltage of the first signal is at a first level and a voltage of the second signal is at a second level and a second period which is after the first period and during which the voltage of the first signal is at a third level and the voltage of the second signal is at a fourth level, the second level being lower than the fourth level if the first level is higher than the third level, the second level being higher than the fourth level if the first level is lower than the third level, and a period during which the second voltage is output to the first word line includes a third period during which the voltage of the first signal is at the third level and the voltage of the second signal is at the fourth level, and a fourth period which is after the third period and during which the voltage of the first signal is at the first level and the voltage of the second signal is at the second level.

12 . The device according to claim 11 , wherein
the first level is higher than the third level, and the second level is lower than the fourth level.

Assignees

• Kioxia Corp

Inventors

• Sakurai Katsuaki
• Kobayashi Osamu
• Kurosawa Tomonori

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/08 Primary

  Address circuits; Decoders; Word-line control circuits · CPC title

• H01L27/11573

  Electricity · mapped topic