Low power static random-access memory

Patent metadata

Field	Value
Publication number	US-2022392512-A1
Application number	US-202117340783-A
Country	US
Kind code	A1
Filing date	Jun 7, 2021
Priority date	Jun 7, 2021
Publication date	Dec 8, 2022
Grant date	—

Abstract

A low power SRAM (static RAM) for an image sensor includes a voltage generation circuit for providing a positive supply voltage V P and a negative supply V N , wherein VDD>V p >V n >V gnd ; a plurality of memory cells coupled to a respective plurality of column sense lines in a pixel array, the plurality of memory cells receiving differential inputs dp and dn; and a Gray counter coupled to switchably couple V P and V N to the differential inputs dp and dn of the plurality of memory cells. A method of operating an image sensor with a low power SRAM includes acquiring an image by the image sensor; generating V P and V N such that V DD >V P >V N >V gnd ; receiving an output g of a column of pixels at a clock input of a memory cell; and switchably coupling V P and V N to the differential inputs dp and dn of a plurality of memory cells in the SRAM according to a codeword from a Gray counter.

First claim

What is claimed is:

1 . A memory circuit comprising:
a voltage generation circuit for providing a positive supply voltage V P and a negative supply V N , wherein V DD >V P >V N >V gnd ; a plurality of memory cells coupled to a respective plurality of column sense lines in a pixel array, the plurality of memory cells receiving differential inputs dp and dn; and a Gray counter coupled to switchably couple V P and V N to the differential inputs dp and dn of the plurality of memory cells.

2 . The memory circuit of claim 1 , further comprising a plurality of switches for coupling V P or V N to differential input dp in accordance with a Gray counter codeword and coupling V P or V N to differential input dn in accordance with an inverse of the Gray counter codeword.

3 . The memory circuit of claim 1 , wherein V P −V N is approximately 100 mV.

4 . The memory circuit of claim 1 , wherein the voltage generation circuit comprises a source follower or voltage buffer.

5 . The memory circuit of claim 1 , wherein the voltage generation circuit comprises a low-dropout regulator.

6 . The memory circuit of claim 1 , wherein the voltage generation circuit comprises a charge pump or switched capacitor circuit.

7 . The memory circuit of claim 1 , wherein V P and V N are generated from V CM , wherein V CM =V T +V OV , V CM is a common mode voltage, and V T and V OV are defined by a voltage generation transistor that matches input transistors in an input latch of the plurality of memory cells.

8 . The memory circuit of claim 1 , wherein the Gray counter counts on each clock transition.

9 . An image sensor comprising:
a plurality of image pixels arranged in rows and columns of a pixel array; a voltage generation circuit for providing a positive supply voltage V P and a negative supply V N , wherein V DD >V P >V N >V gnd ; and a low power SRAM comprising:
a plurality of memory cells coupled to a respective plurality of columns in a pixel array, the plurality of memory cells receiving differential inputs dp and dn; and
a Gray counter for switchably coupling V P and V N to the differential inputs dp and dn of the plurality of memory cells.

10 . The image sensor of claim 9 , further comprising a plurality of switches for coupling V P or V N to differential input dp in accordance with a Gray counter codeword and coupling V P or V N to differential input dn in accordance with an inverse of the Gray counter codeword.

11 . The image sensor of claim 9 , wherein V P −V N is approximately 100 mV.

12 . The image sensor of claim 9 , wherein the voltage generation circuit comprises a source follower or voltage buffer.

13 . The image sensor of claim 9 , wherein the voltage generation circuit comprises a low-dropout regulator.

14 . The image sensor of claim 9 , wherein the voltage generation circuit comprises a charge pump or a switched capacitor circuit.

15 . The image sensor of claim 9 , wherein V P and V N are generated from V CM , wherein V CM =V T +V OV , V CM is a common mode voltage, and V T and V OV are defined by a voltage generation transistor that matches input transistors in an input latch of the plurality of memory cells.

16 . A method of operating an image sensor comprising image pixels arranged in rows and columns of a pixel array, and a low power SRAM comprising a plurality of memory cells coupled to corresponding columns of image pixels in the pixel array, the plurality of memory cells receiving differential inputs dp and dn; a voltage generation circuit for providing a positive supply voltage V P and a negative supply V N and a Gray counter, the method comprising:
acquiring an image by the image pixels; generating V P and V N such that V DD >V P >V N >V gnd ; receiving an output g of a column of pixels at a clock input of a memory cell; and switchably coupling V P and V N to the differential inputs dp and dn of the plurality of memory cells according to a codeword from the Gray counter.

17 . The method of claim 16 , wherein V P and V N are generated from V CM , wherein V CM =V T +V OV , V CM is a common mode voltage, and V T and V OV are defined by a voltage generation transistor that matches input transistors in an input latch of the plurality of memory cells.

18 . The method of claim 16 , wherein V P and V N are generated using a voltage generation circuit comprising a source follower, voltage buffer or low-dropout regulator.

19 . The method of claim 16 , wherein, wherein V P and V N are generated using a voltage generation circuit comprising a charge pump or a switched capacitor circuit.

20 . The method of claim 16 , wherein V P −V N is approximately 100 mV.

Assignees

• Omnivision Tech Inc

Inventors

• Johansson Robert

Classifications

• H03K23/005 Primary

  using minimum change code, e.g. Gray Code · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/1087

  Data input latches · CPC title

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title