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Semiconductor transistor structure with reduced contact resistance and fabrication method thereof
US2022367694A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2022367694-A1 |
| Application number | US-202117330420-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 26, 2021 |
| Priority date | May 11, 2021 |
| Publication date | Nov 17, 2022 |
| Grant date | — |
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Abstract
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A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmic contact metal is disposed in the recess. The Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess.
First claim
Opening claim text (preview).
What is claimed is: 1 . A semiconductor transistor structure with reduced contact resistance, comprising: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer; a recess in a contact region, wherein the recess penetrates through the barrier layer and extends into the channel layer; and an Ohmic contact metal disposed in the recess, wherein the Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer in the recess and in direct contact with an inclined side surface of the 2DEG layer and the channel layer in the recess. 2 . The semiconductor transistor structure with reduced contact resistance according to claim 1 , wherein the inclined side surface is inclined at an angle ranging between 60-80 degrees with a horizontal plane. 3 . The semiconductor transistor structure with reduced contact resistance according to claim 1 , wherein the channel layer comprises a GaN layer. 4 . The semiconductor transistor structure with reduced contact resistance according to claim 1 , wherein the barrier layer comprises an AlGaN layer. 5 . The semiconductor transistor structure with reduced contact resistance according to claim 4 , wherein the barrier layer further comprises an AlN layer. 6 . The semiconductor transistor structure with reduced contact resistance according to claim 1 further comprising: a passivation layer on the barrier layer. 7 . The semiconductor transistor structure with reduced contact resistance according to claim 1 , wherein a depth of the recess is about 10 nm below a bottom surface of the barrier layer. 8 . The semiconductor transistor structure with reduced contact resistance according to claim 1 , wherein the Ohmic contact metal comprises Ti and Al. 9 . A semiconductor transistor structure with reduced contact resistance, comprising: a substrate; a channel layer on the substrate; a barrier layer on the channel layer; a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer; a recess in a contact region, wherein the recess penetrates through the barrier layer and extends into the channel layer; and an Ohmic contact metal disposed in the recess, wherein the Ohmic contact metal is in direct contact with a vertical side surface of the barrier layer and the 2DEG layer in the recess and in direct contact with an inclined side surface of the channel layer in the recess. 10 . The semiconductor transistor structure with reduced contact resistance according to claim 9 , wherein the inclined side surface is inclined at an angle ranging between 60-80 degrees with a horizontal plane. 11 . The semiconductor transistor structure with reduced contact resistance according to claim 9 , wherein the channel layer comprises a GaN layer. 12 . The semiconductor transistor structure with reduced contact resistance according to claim 9 , wherein the barrier layer comprises an AlGaN layer. 13 . The semiconductor transistor structure with reduced contact resistance according to claim 12 , wherein the barrier layer further comprises an AlN layer. 14 . The semiconductor transistor structure with reduced contact resistance according to claim 9 further comprising: a passivation layer on the barrier layer. 15 . The semiconductor transistor structure with reduced contact resistance according to claim 9 , wherein a depth of the recess is about 10 nm below a bottom surface of the barrier layer. 16 . The semiconductor transistor structure with reduced contact resistance according to claim 9 , wherein the Ohmic contact metal comprises Ti and Al. 17 . A method of forming a semiconductor transistor structure with reduced contact resistance, comprising: providing a substrate; forming a channel layer on the substrate; forming a barrier layer on the channel layer, thereby forming a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer; forming a recess in a contact region, wherein the recess penetrates through the barrier layer and extends into the channel layer, wherein the recess has a vertical sidewall profile in the barrier layer and an angled sidewall profile in the channel layer; and forming an Ohmic contact metal in the recess, wherein the Ohmic contact metal is in direct contact with the barrier layer, the 2DEG layer and the channel layer in the recess. 18 . The method according to claim 17 , wherein the angled sidewall profile in the channel layer comprises an inclined side surface that is inclined at an angle ranging between 60-80 degrees with a horizontal plane. 19 . The method according to claim 17 , wherein the angled sidewall profile is also formed in the 2DEG layer. 20 . The method according to claim 17 , wherein the vertical sidewall profile is also formed in the 2DEG layer.
Assignees
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Classifications
- H01L29/7783Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US2022367694A1 cover?
- A semiconductor transistor structure with reduced contact resistance includes a substrate, a channel layer on the substrate, a barrier layer on the channel layer, a two-dimensional electron gas (2DEG) layer at an interface between the barrier layer and the channel layer, and a recess in a contact region. The recess penetrates through the barrier layer and extends into the channel layer. An Ohmi…
- Who is the assignee on this patent?
- United Microelectronics Corp
- What technology area does this patent fall under?
- Primary CPC classification H01L29/7783. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Nov 17 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).