Semiconductor package

Patent metadata

Field	Value
Publication number	US-2022367553-A1
Application number	US-202217745010-A
Country	US
Kind code	A1
Filing date	May 16, 2022
Priority date	May 17, 2021
Publication date	Nov 17, 2022
Grant date	—

Abstract

A semiconductor package including a substrate including a through hole, an image sensor structure on the substrate, and a first transparent substrate on the substrate and spaced apart from the image sensor structure may be provided. The image sensor structure includes a logic chip on the substrate, a first sensing chip on an active surface of the logic chip, and a second sensing chip on an inactive surface of the logic chip and connected to the active surface of the logic chip through a first via that vertically penetrates the logic chip. On a bottom surface of the logic chip, at least a portion of one of the first sensing chip and the second sensing chip is in the through hole.

First claim

1 . A semiconductor package, comprising:
a substrate including a through hole; an image sensor structure on the substrate; and a first transparent substrate on the substrate and spaced apart from the image sensor structure, wherein the image sensor structure includes,
a logic chip on the substrate,
a first sensing chip on an active surface of the logic chip, and
a second sensing chip on an inactive surface of the logic chip, the second sensing chip connected to the active surface of the logic chip through a first via that vertically penetrates the logic chip, and
wherein, on a bottom surface of the logic chip, at least a portion of one of the first sensing chip and the second sensing chip is in the through hole.

2 . The semiconductor package of claim 1 , wherein
the active surface of the logic chip faces the substrate, and at least a portion of the first sensing chip is in the through hole of the substrate.

3 . The semiconductor package of claim 2 , wherein
a first connection terminal is on the bottom surface of the logic chip, and the logic chip is mounted on the substrate through the first connection terminal.

4 . The semiconductor package of claim 3 , wherein
the first connection terminal is between the substrate, and when viewed in a plan view, the logic chip is outside the through hole.

5 . The semiconductor package of claim 1 , wherein
the active surface of the logic chip faces the first transparent substrate, and at least a portion of the second sensing chip is in the through hole of the substrate.

6 . The semiconductor package of claim 5 , wherein
the logic chip is mounted on the substrate through a second via and a first connection terminal, the second via vertically penetrates the logic chip and is connected to the active surface of the logic chip, and the first connection terminal is on the bottom surface of the logic chip and connects the second via and the substrate to each other.

7 . The semiconductor package of claim 5 , wherein the logic chip is mounted on the substrate through a connection wire that connects the substrate to a top surface of the logic chip.

8 . The semiconductor package of claim 5 , wherein the logic chip is attached to the substrate through an adhesion layer that is on the bottom surface of the logic chip.

9 . The semiconductor package of claim 1 , wherein
the first sensing chip and the logic chip are bonded each other in direct bonding manner, a dielectric pattern of the first sensing chip and a dielectric pattern of the logic chip are in contact with each other to constitute a single body, or a pad of the first sensing chip and a pad of the logic chip are in contact with each other to constitute a single body.

10 . The semiconductor package of claim 1 , wherein the first sensing chip and the logic chip are connected to each other through a connection terminal between the first sensing chip and the logic chip.

11 . The semiconductor package of claim 1 , wherein
the substrate has a recess region that extends into the substrate from a bottom surface of the substrate, a width of the recess region being greater than a width of the through hole, the through hole of the substrate penetrates a central portion of the recess region, and a second transparent substrate is provided in the recess region.

12 . (canceled)

13 . (canceled)

14 . The semiconductor package of claim 1 , wherein the first transparent substrate is spaced apart from the image sensor structure by a spacer between the first transparent substrate and the substrate.

15 . The semiconductor package of claim 1 , wherein
the image sensor structure further includes a memory chip between the logic chip and the second sensing chip, the first via penetrates the memory chip and the logic chip from the second sensing chip and connected to the active surface of the logic chip, and the first sensing chip is connected to the memory chip through a second via that vertically penetrates the first sensing chip and the logic chip.

16 . The semiconductor package of claim 1 , wherein
the image sensor structure further includes a memory chip between the logic chip and the first sensing chip, the second sensing chip is connected to the memory chip through a second via that vertically penetrates the second sensing chip and the logic chip.

17 . (canceled)

18 . A semiconductor package, comprising:
a substrate having a through hole and a recess region, the through hole penetrating the substrate, the recess region being on a lower portion of the substrate; a logic chip on the substrate and covering the through hole; a first sensing chip on the logic chip; a second sensing chip below the logic chip and positioned in the through hole; a first transparent substrate on the substrate; a spacer between the substrate and the first transparent substrate, the spacer separating the first transparent substrate and the first sensing chip from each other; and a second transparent substrate in the recess region of the substrate, wherein one of the first sensing chip and the second sensing chip is connected to an active surface of the logic chip through a first via that vertically penetrates the logic chip, and wherein the other of the first sensing chip and the second sensing chip is on the active surface of the logic chip.

19 . The semiconductor package of claim 18 , wherein
the active surface of the logic chip faces the first transparent substrate, and the second sensing chip is connected to the active surface of the logic chip by the first via.

20 . The semiconductor package of claim 18 , wherein
the active surface of the logic chip faces the second transparent substrate, and the first sensing chip is connected to the active surface of the logic chip by the first via.

21 . The semiconductor package of claim 18 , wherein
a connection terminal is between the substrate and the logic chip and outside the through hole, and the logic chip is mounted on the substrate through the connection terminal.

22 . The semiconductor package of claim 18 , wherein
the logic chip is attached to the substrate through an adhesion layer, and the logic chip is mounted on the substrate through a connection wire that connects a top surface of the logic chip to a top surface of the substrate.

23 .- 28 . (canceled)

29 . A semiconductor package, comprising:
a substrate; a chip stack on the substrate; and a first transparent substrate on the chip stack, wherein the chip stack includes,
a first semiconductor chip on a top surface of the substrate;
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip on an active surface of the first semiconductor chip; and
a third semiconductor chip below the first semiconductor chip, the third semiconductor chip penetrating a central portion of the substrate and being exposed by a bottom surface of the substrate,
wherein a first pad of the first semiconductor chip is in direct contact with a second pad of the second semiconductor chip, wherein the third semiconductor chip is coupled to the active surface of the first semiconductor chip through a first via that vertically penetrates the first semiconductor chip, wherein the first semiconductor chip includes a logic chip, and wherein the second semiconductor chip includes an image sensing chip.

30 .- 38 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Kyungkyu
• Lee Dong-Hun
• Kim Woonbae
• Lee Daeho
• Lee Jungpil

Classifications

• H10F39/811

  Interconnections · CPC title

• H10F39/809 Primary

  of hybrid image sensors · CPC title

• H10F39/182

  Colour image sensors · CPC title

• H01L27/14645

  Electricity · mapped topic

• H01L27/14634 Primary

  Electricity · mapped topic