Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-2022352316-A1
Application number	US-202217865400-A
Country	US
Kind code	A1
Filing date	Jul 15, 2022
Priority date	Aug 24, 2020
Publication date	Nov 3, 2022
Grant date	—

Abstract

Provided is a semiconductor device including a drift region, a base region, two trench portions and a mesa portion, wherein at least one of the two trench portions is a gate trench portion, the mesa portion includes: a first conductivity type emitter region provided to be exposed on an upper surface of the mesa portion; a second conductivity type contact region provided to be exposed on the upper surface of the mesa portion alternately with the emitter region in an extending direction; and a second conductivity type connecting region with a higher doping concentration than the base region, wherein the connecting region is provided to overlap with the emitter region in a top view, is arranged apart from the gate trench portion, is arranged below the upper surface of the mesa portion, and connects two of the contact regions sandwiching the emitter region in the extending direction.

First claim

What is claimed is:

1 . A semiconductor device comprising a semiconductor substrate, wherein
the semiconductor substrate includes: a first conductivity type drift region; a second conductivity type base region provided between the drift region and an upper surface of the semiconductor substrate; two trench portions which are provided to extend in a predetermined extending direction on the upper surface of the semiconductor substrate, and provided from the upper surface of the semiconductor substrate to the drift region; and a mesa portion provided between the two trench portions, wherein at least one of the two trench portions is a gate trench portion, and the mesa portion includes: a first conductivity type emitter region having a higher doping concentration than the drift region, which is provided to be exposed on the upper surface of the mesa portion and provided to contact both of the two trench portions; a second conductivity type contact region provided to be exposed on the upper surface of the mesa portion alternately with the emitter region in the extending direction, and provided to contact both of the two trench portions; and a second conductivity type connecting region with a higher doping concentration than the base region, wherein the connecting region is provided to overlap with the emitter region in a top view, arranged apart from the gate trench portion, arranged below the upper surface of the mesa portion, and connects two of the contact regions sandwiching the emitter region in the extending direction.

2 . The semiconductor device according to claim 1 , wherein the connecting region is in contact with a lower end of the emitter region.

3 . The semiconductor device according to claim 1 , wherein at least a part of the connecting region is arranged inside the emitter region.

4 . The semiconductor device according to claim 1 , wherein the connecting region is arranged below a lower end of the emitter region.

5 . The semiconductor device according to claim 1 , wherein a doping concentration of the connecting region is higher than a doping concentration of the contact region.

6 . The semiconductor device according to claim 1 , wherein
the connecting region includes a second conductivity type dopant which is different from a second conductivity type dopant of the base region.

7 . The semiconductor device according to claim 6 , wherein the dopant of the connecting region has a lower diffusion coefficient on the semiconductor substrate than the dopant of the base region.

8 . The semiconductor device according to claim 1 , wherein
both of the two trench portions are the gate trench portions, and the connecting region is arranged at a center between the two trench portions.

9 . The semiconductor device according to claim 1 , wherein
one of the two trench portions is the gate trench portion and the other is a dummy trench portion, and the connecting region is arranged, between the two trench portions, closer to the dummy trench portion.

10 . The semiconductor device according to claim 1 , wherein
each of the contact region and the connecting region has a concentration peak of a doping concentration in a depth direction of the semiconductor substrate, and the concentration peak of the contact region is arranged closer to the upper surface side of the semiconductor substrate than the concentration peak of the connecting region.

11 . The semiconductor device according to claim 2 , wherein a doping concentration of the connecting region is higher than a doping concentration of the contact region.

12 . The semiconductor device according to claim 3 , wherein a doping concentration of the connecting region is higher than a doping concentration of the contact region.

13 . The semiconductor device according to claim 4 , wherein a doping concentration of the connecting region is higher than a doping concentration of the contact region.

14 . The semiconductor device according to claim 2 , wherein the connecting region includes a second conductivity type dopant which is different from a second conductivity type dopant of the base region.

15 . The semiconductor device according to claim 3 , wherein the connecting region includes a second conductivity type dopant which is different from a second conductivity type dopant of the base region.

16 . The semiconductor device according to claim 4 , wherein the connecting region includes a second conductivity type dopant which is different from a second conductivity type dopant of the base region.

17 . The semiconductor device according to claim 5 , wherein the connecting region includes a second conductivity type dopant which is different from a second conductivity type dopant of the base region.

18 . A manufacturing method of a semiconductor device, comprising:
firstly forming, on a semiconductor substrate which has a first conductivity type drift region: a second conductivity type base region provided between the drift region and an upper surface of the semiconductor substrate; two trench portions provided to extend in a predetermined extending direction on the upper surface of the semiconductor substrate, and provided from the upper surface of the semiconductor substrate to the drift region; a mesa portion provided between the two trench portions, a first conductivity type emitter region having a higher doping concentration than the drift region, which is exposed on the upper surface of the mesa portion and contacting both of the two trench portions; and a second conductivity type contact region which is exposed on the upper surface of the mesa portion alternately with the emitter region in the extending direction, and contacting both of the two trench portions, and secondly forming a second conductivity type connecting region with a higher doping concentration than the base region, wherein the connecting region overlaps with the emitter region in a top view, is arranged below the upper surface of the mesa portion, and connects two of the contact regions sandwiching the emitter region in the extending direction; wherein at least one of the two trench portions is a gate trench portion, and the method comprises forming the connecting region apart from the gate trench portion in the secondly forming.

19 . The manufacturing method according to claim 18 , wherein in the secondly forming, the connecting region is formed by masking a region in which the contact region is formed, and then implanting a second conductivity type dopant on the semiconductor substrate.

20 . The manufacturing method according to claim 18 , wherein in the secondly forming, the connecting region is formed by implanting a second conductivity type dopant into a region in which the connecting region is to be formed and at least a partial region of a region in which the contact region is formed.

Assignees

• Fuji Electric Co Ltd

Inventors

• KARAMOTO Yuki

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D84/811

  Combinations of field-effect devices and one or more diodes, capacitors or resistors · CPC title

• H01L29/66348

  Electricity · mapped topic