Pixel circuit and display device including the same

Patent metadata

Field	Value
Publication number	US-2022351673-A1
Application number	US-202217669887-A
Country	US
Kind code	A1
Filing date	Feb 11, 2022
Priority date	Apr 29, 2021
Publication date	Nov 3, 2022
Grant date	—

Abstract

A panel repairing method includes detecting a defective portion of a panel, providing primary ink, which is ejected from an ink ejection pin, onto a first portion of the defective portion, spreading the primary ink in a direction parallel to a plane defined on the panel, temporarily curing the primary ink, providing secondary ink, which is ejected from the ink ejection pin, onto a second portion of the defective portion disposed adjacent to the first portion, and curing the primary ink and the secondary ink.

First claim

1 . A pixel circuit comprising:
a first transistor including a first gate terminal, a first source terminal electrically connected to a first node, a first drain terminal electrically connected to a light emitting diode, and a back-gate terminal, wherein a first voltage which decreases over time is applied to the back-gate terminal; and a second transistor including a second gate terminal which receives a gate signal, a second source terminal which receives a data voltage, and a second drain terminal electrically connected to the first node.

2 . The pixel circuit of claim 1 , wherein a driving range of the first transistor increases over time.

3 . The pixel circuit of claim 1 , wherein the back-gate terminal is electrically connected to a global transistor, and
the global transistor includes a global gate terminal which receives a second voltage which has a negative polarity, a global source terminal which receives a third voltage which has a positive polarity, and a global drain terminal electrically connected to the back-gate terminal.

4 . The pixel circuit of claim 3 , wherein the global drain terminal provides the first voltage to the back-gate terminal.

5 . The pixel circuit of claim 3 , the pixel circuit further comprising:
a light emission control transistor including a light emission control gate terminal which receives a light emission driving signal, a light emission control source terminal which receives a high power voltage, and a light emission control drain terminal electrically connected to the first node, and wherein the third voltage is the high power voltage.

6 . The pixel circuit of claim 3 , wherein a terminal of the light emitting diode receives a low power voltage, and
the second voltage is the low power voltage.

7 . The pixel circuit of claim 3 , further comprising:
an initialization transistor including an initialization gate terminal which receives an initialization gate signal, an initialization source terminal electrically connected to the gate terminal of the first transistor, and an initialization drain terminal which receives a transistor initialization voltage, and wherein the second voltage is the transistor initialization voltage.

8 . The pixel circuit of claim 3 , further comprising:
an anode initialization transistor including an anode initialization gate terminal which receives a bypass gate signal, an anode initialization source terminal electrically connected to the light emitting diode, and an anode initialization drain terminal which receives an anode initialization voltage, and wherein the second voltage is the anode initialization voltage.

9 . A display device comprising:
a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns; a gate driving circuit which applies a gate signal to the pixel circuits; a data driving circuit which applies a data voltage to the pixel circuits; and a control circuit which controls the gate driving circuit and the data driving circuit, and wherein each of the pixel circuits includes: a first transistor including a first gate terminal, a first source terminal electrically connected to a first node, a first drain terminal electrically connected to a light emitting diode, and a back-gate terminal which receives a first voltage which decreases over time; and a second transistor including a second gate terminal which receives a gate signal, a second source terminal which receives a data voltage, and a second drain terminal electrically connected to the first node.

10 . The display device of claim 9 , wherein a driving range of the first transistor increases over time.

11 . The display device of claim 9 , further comprising:
a plurality of global transistors, wherein each of the global transistors includes a global gate terminal which receives a second voltage which has a negative polarity, a global source terminal which receives a third voltage which has a positive polarity, and a global drain terminal electrically connected to the back-gate terminal, and the each of the global transistors is electrically connected to the pixel circuits which correspond to at least one column among the plurality of columns.

12 . The display device of claim 11 , wherein the global drain terminal provides the first voltage to the back-gate terminal.

13 . A display device comprising:
a substrate; a driving transistor including an active pattern disposed on the substrate and including a channel region, a gate electrode disposed on the active pattern and overlapping the channel region in a plan view, and a back-gate pattern disposed under the active pattern and overlapping the active pattern in the plan view; and a global transistor which provides a first voltage which decreases over time to the back-gate pattern.

14 . The display device of claim 13 , wherein the global transistor includes:
a global active pattern including a global source region electrically connected to a voltage supply line which provides a third voltage which has a positive polarity, a global drain region electrically connected to the back-gate pattern, and a global channel region disposed between the global source region and the global drain region; and a global gate electrode disposed on the global active pattern, and which overlaps the global channel region in the plan view, and receives a second voltage which has a negative polarity.

15 . The display device of claim 13 , wherein the voltage supply line is a high power voltage line.

16 . The display device of claim 14 , further comprising:
a light emitting diode electrically connected to the driving transistor and which receives a low power voltage, and wherein the second voltage is the low power voltage.

17 . The display device of claim 14 , further comprising:
an initialization transistor including an initialization gate terminal which receives an initialization gate signal, an initialization source terminal electrically connected to the gate electrode of the driving transistor, and an initialization drain terminal which receives a transistor initialization voltage, and wherein the second voltage is the transistor initialization voltage.

18 . The display device of claim 14 , further comprising:
a light emitting diode electrically connected to the driving transistor, and an anode initialization transistor including an anode initialization gate terminal which receives a bypass gate signal, an anode initialization source terminal electrically connected to the light emitting diode, and an anode initialization drain terminal which receives an anode initialization voltage, and wherein the second voltage is the anode initialization voltage.

Assignees

• Samsung Display Co Ltd

Inventors

• Kim Keunwoo

Classifications

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2330/028

  Generation of voltages supplied to electrode drivers in a matrix display other than LCD · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title