Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022344455-A1
Application number	US-202217682687-A
Country	US
Kind code	A1
Filing date	Feb 28, 2022
Priority date	Apr 23, 2021
Publication date	Oct 27, 2022
Grant date	—

Abstract

A FLR structure is provided in an edge termination region as a voltage withstanding structure. The FLR structure is configured by multiple FLRs that concentrically surround a periphery of an active region. An impurity concentration of the FLRs is less than 1×1018/cm3 or preferably, may be in a range of 3×1017/cm3 to 9×1017/cm3. A thickness of each of the FLRs is in a range of 0.7 μm to 1.1 μm. A first interval between an innermost FLR and an outer peripheral pt-type region is at most about 1.2 μm.

First claim

What is claimed is:

1 . A semiconductor device having an active region through which a main current flows and a termination region surrounding a periphery of the active region, the semiconductor device comprising:
a semiconductor substrate containing a semiconductor having a band gap wider than a band gap of silicon, the semiconductor substrate having a first main surface and a second main surface opposite to each other; a first semiconductor region of a first conductivity type, provided in the semiconductor substrate; a second semiconductor region of a second conductivity type, provided in the active region, between the first main surface of the semiconductor substrate and the first semiconductor region; a device element structure formed in the active region, and including a pn junction between the second semiconductor region and the first semiconductor region; a first electrode electrically connected to the second semiconductor region; a second electrode provided on the second main surface of the semiconductor substrate; and a plurality of second-conductivity-type voltage withstanding regions selectively provided apart from one another in the first semiconductor region, in surface regions of the semiconductor substrate at the first main surface thereof in the termination region, the second-conductivity-type voltage withstanding regions each concentrically surrounding the periphery of the active region, wherein the second-conductivity-type voltage withstanding regions have an impurity concentration that is less than 1×10 18 /cm 3 , and the second-conductivity-type voltage withstanding regions have a thickness in a range of 0.7 μm to 1.1 μm.

2 . The semiconductor device according to claim 1 , wherein the impurity concentration of the second-conductivity-type voltage withstanding regions is in a range of 3×10 17 /cm 3 to 9×10 17 /cm 3 .

3 . The semiconductor device according to claim 1 , the comprising a second-conductivity-type high-concentration region selectively provided between the second semiconductor region and the first semiconductor region, and in contact with the second semiconductor region, the second-conductivity-type high-concentration region surrounding the periphery of the active region and having an impurity concentration higher than an impurity concentration of the second semiconductor region, wherein
the second-conductivity-type high-concentration region is provided between the active region and the second-conductivity-type voltage withstanding regions and faces the second-conductivity-type voltage withstanding regions in a direction parallel to the first main surface of the semiconductor substrate.

4 . The semiconductor device according to claim 3 , wherein a first interval between the second-conductivity-type high-concentration region and an innermost one of the second-conductivity-type voltage withstanding regions is at most 1.2 μm, the innermost one being closest among the second-conductivity-type voltage withstanding regions to the active region.

5 . The semiconductor device according to claim 3 , wherein an innermost one of the second-conductivity-type voltage withstanding regions is in contact with the second-conductivity-type high-concentration region, the innermost one being closest among the second-conductivity-type voltage withstanding regions to the active region.

6 . The semiconductor device according to claim 5 , wherein a second interval between the innermost one of the second-conductivity-type voltage withstanding regions and a second one of the second-conductivity-type voltage withstanding regions is at most 2.1 μm, the second one being second among the second-conductivity-type voltage withstanding regions from the active region.

7 . The semiconductor device according to claim 5 , wherein among the second-conductivity-type voltage withstanding regions, a third interval between a second one of the second-conductivity-type voltage withstanding regions and a third one of the second-conductivity-type voltage withstanding regions is at most 3.1 μm, the second one being second from the active region and the third one being third from the active region.

8 . The semiconductor device according to claim 7 , wherein the third interval is at most 1.0 μm.

9 . The semiconductor device according to claim 8 , wherein among the second-conductivity-type voltage withstanding regions, a fourth interval between the third one of the second-conductivity-type voltage withstanding regions and a fourth one of the second-conductivity-type voltage withstanding regions is at most 2.0 μm, the fourth one being fourth from the active region.

10 . The semiconductor device according to claim 4 , wherein an interval between an adjacent two of the second-conductivity-type voltage withstanding regions at least fourth from the active region and adjacent to each other is wider than the first interval.

11 . The semiconductor device according to claim 1 , wherein the second-conductivity-type voltage withstanding regions all have a same width that is a shortest length of the second-conductivity-type voltage withstanding regions in a direction parallel to the first main surface of the semiconductor substrate.

12 . The semiconductor device according to claim 1 , wherein each second-conductivity-type voltage withstanding region has a width that is a shortest length of said each second-conductivity-type voltage withstanding region in a direction parallel to the first main surface of the semiconductor substrate, and
the width of a second and subsequent ones of the second-conductivity-type voltage withstanding regions at least second from the active region is wider than the width of an innermost one of the second-conductivity-type voltage withstanding regions closest to the active region.

13 . The semiconductor device according to claim 1 , wherein the second-conductivity-type voltage withstanding regions reach the first main surface of the semiconductor substrate.

14 . The semiconductor device according to claim 1 , wherein
the second-conductivity-type voltage withstanding regions are provided at a depth position apart from the first main surface of the semiconductor substrate, and the first semiconductor region intervenes between the first main surface of the semiconductor substrate and the second-conductivity-type voltage withstanding regions.

15 . The semiconductor device according to claim 1 , wherein the second-conductivity-type voltage withstanding regions each have, in a cross-sectional view thereof, a rectangular shape or a barrel-like shape having a width that is relatively wider at a center position in a depth direction.

16 . The semiconductor device according to claim 1 , wherein a portion of the first main surface of the semiconductor substrate in the termination region is free of a conductive film.

17 . The semiconductor device according to claim 1 , wherein a portion of the first main surface of the semiconductor substrate in the termination region is covered by an insulating layer.

Assignees

• Fuji Electric Co Ltd

Inventors

• Hoshi Yasuyuki
• Moriya Tomohiro

Classifications

• H01L29/0619 Primary

  Electricity · mapped topic

• H01L29/7811

  Electricity · mapped topic

• H01L29/1608

  Electricity · mapped topic

• H10D62/8325

  Silicon carbide · CPC title

• H10D30/665

  having edge termination structures · CPC title