Semiconductor device and manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-2022344366-A1
Application number	US-202117482797-A
Country	US
Kind code	A1
Filing date	Sep 23, 2021
Priority date	Apr 23, 2021
Publication date	Oct 27, 2022
Grant date	—

Abstract

A semiconductor device includes a gate structure including conductive layers and insulating layers alternately stacked with each other, channel structures passing through the gate structure and arranged in a first direction, a cutting structure extending in the first direction and passing through the channel structures, and a first slit structure passing through the gate structure and extending in a second direction crossing the first direction.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a gate structure including conductive layers and insulating layers alternately stacked with each other; channel structures passing through the gate structure and arranged in a first direction; a cutting structure extending in the first direction and passing through the channel structures; and a first slit structure passing through the gate structure and extending in a second direction crossing the first direction.

2 . The semiconductor device of claim 1 , wherein each of the channel structures is separated into a first channel structure and a second channel structure by the cutting structure.

3 . The semiconductor device of claim 2 , further comprising:
at least one first bit line extending in the first direction and coupled to first channel structures; and at least one second bit line extending in the first direction and coupled to second channel structures.

4 . The semiconductor device of claim 1 , further comprising a second slit structure passing through the gate structure at a shallower depth than both the first slit structure and the cutting structure, the second slit structure extending in the second direction.

5 . The semiconductor device of claim 4 , wherein the cutting structure and the second slit structure contact each other.

6 . The semiconductor device of claim 1 , wherein the cutting structure includes an insulating material.

7 . A semiconductor device, comprising:
a gate structure including conductive layers and insulating layers alternately stacked with each other; pillar structures passing through the gate structure; a cutting structure passing through the pillar structures and separating each of the pillar structures into a first pillar structure and a second pillar structure; a first slit structure passing through the gate structure and extending in a direction crossing the cutting structure; a first interconnection line extending in a direction crossing the first slit structure, the first interconnection line coupled to the first pillar structures; and a second interconnection line extending in a direction crossing the first slit structure, the second interconnection line coupled to the second pillar structures.

8 . The semiconductor device of claim 7 , further comprising:
first contact plugs coupled to the first pillar structures, respectively, the first contact plugs coupling the first pillar structures to the first interconnection line; and second contact plugs coupled to the second pillar structures, respectively, the second contact plugs coupling the second pillar structures to the second interconnection line.

9 . A method of manufacturing a semiconductor device, the method comprising:
forming a stacked structure; forming channel structures passing through the stacked structure and arranged in a first direction; forming a cutting structure passing through the channel structures and extending in the first direction; and forming a first slit structure passing through the stacked structure and extending in a second direction crossing the first direction.

10 . The method of claim 9 , wherein forming the cutting structure comprises etching the channel structures so that each of the channel structures is separated into a first channel structure and a second channel structure.

11 . The method of claim 10 , further comprising:
forming at least one first bit line extending in the first direction and coupled to first channel structures; and forming at least one second bit line extending in the first direction and coupled to second channel structures.

12 . The method of claim 9 , wherein forming the cutting structure comprises:
forming a trench crossing at least two channel structures; and forming the cutting structure to include an insulating material in the trench.

13 . The method of claim 9 , wherein forming of the first slit structure comprises:
forming a first slit passing through the stacked structure including alternately stacked first material layers and second material layers, the first slit extending in the second direction; replacing the first material layers with third material layers through the first slit; and forming the first slit structure in the first slit.

14 . The method of claim 9 , further comprising forming a second slit structure passing through the stacked structure at a shallower depth than the first slit structure and extending in the second direction.

15 . The method of claim 14 , wherein forming the second slit structure comprises:
forming a second slit by etching the stacked structure and the cutting structure; and forming the second slit structure in the second slit.

Assignees

• Sk Hynix Inc

Inventors

• Park Mi Seong
• Kim Jang Won
• Park In Su
• Jang Jung Shik
• Choi Won Geun
• Choi Jung Dal

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic