Integrated circuit layout

Patent metadata

Field	Value
Publication number	US-2022344321-A1
Application number	US-202117348784-A
Country	US
Kind code	A1
Filing date	Jun 16, 2021
Priority date	Apr 26, 2021
Publication date	Oct 27, 2022
Grant date	—

Abstract

An integrated circuit layout includes a first standard cell and a second standard cell. The first standard cell includes first gate lines arranged along a first direction and extending along a second direction. The second standard cell abuts to one side of the first standard cell along the second direction and includes second gate lines arranged along the first direction and extending along the second direction. A first gate line width of the first gate lines and a second gate line width of the second gate lines are different. A first cell width of the first standard cell and a second cell width of the second standard cell are integral multiples of a default gate line pitch of the first gate lines and the second gate lines. At least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

First claim

What is claimed is:

1 . An integrated circuit layout, comprising:
a first standard cell, comprising:
two first cell boundaries arranged in parallel in a first direction and extending along a second direction, wherein the first direction and the second direction are perpendicular; and
a plurality of first gate lines between the two first cell boundaries and arranged along the first direction, wherein the first gate lines respectively comprise a first gate line width and are distanced from each other by a default gate line pitch; and
a second standard cell abutting to a side of the first standard cell along the second direction and comprising:
two second cell boundaries arranged in parallel in the first direction and extending along the second direction; and
a plurality of second gate lines between the two second cell boundaries and arranged along the first direction, wherein the second gate lines respectively comprise a second gate line width and are distanced from each other by the default gate line pitch, the first gate line width and the second gate line width are different, a first cell width between the two first cell boundaries and a second cell width between the two second cell boundaries are integral multiples of the default gate line pitch, and at least some of the second gate lines and at least some of the first gate lines are aligned along the second direction.

2 . The integrated circuit layout according to claim 1 , wherein the two second cell boundaries are respectively aligned to one of the first gate lines or one of the two first cell boundaries.

3 . The integrated circuit layout according to claim 1 , wherein the two first cell boundaries are equally distanced from the first gate lines, and the two second cell boundaries are equally distanced from the second gate lines.

4 . The integrated circuit layout according to claim 1 , further comprising a plurality of dummy gate lines overlapping the first cell boundaries and the second cell boundaries, wherein the dummy gate lines are aligned to the first gate lines or the second gate lines along the second direction.

5 . The integrated circuit layout according to claim 4 , wherein each of the dummy gate lines is divided into two equal portions by the first cell boundaries or the second cell boundaries.

6 . The integrated circuit layout according to claim 4 , wherein a dummy gate line width of the dummy gate lines equals to the first gate line width or the second gate line width.

7 . The integrated circuit layout according to claim 4 , wherein a dummy gate line width of the dummy gate lines is different from the first gate line width and the second gate line width.

8 . The integrated circuit layout according to claim 4 , wherein:
the second gate line width equals to a sum of the first gate line width and a variable; the first gate lines comprise a first gate line space between edges of the first gate lines, the second gate lines comprise a second gate line space between the edges of the second gate lines, wherein the second gate line space is smaller than the first gate line space by the variable; and an edge of the dummy gate lines and an edge of the first gate lines adjacent to the edge of the dummy gate lines comprise a first dummy gate line space, another edge of the dummy gate lines and an edge of the second gate lines adjacent to the another edge of the dummy gate lines comprise a second dummy gate line space, wherein the second dummy gate line space is smaller than the first dummy gate line space by 0.5 of the variable.

9 . The integrated circuit layout according to claim 4 , wherein the first standard cell further comprises a plurality of first active region patterns extending along the first direction and arranged in parallel along the second direction, the second standard cell further comprises a plurality of second active region patterns extending along the first direction and arranged in parallel along the second direction, wherein distal ends of the first active region patterns and the second active region patterns are overlapped by the first gate lines, the second gate lines, and the dummy gate lines.

10 . The integrated circuit layout according to claim 9 , wherein the first active region patterns and the second active region patterns have a same width in the second direction.

11 . The integrated circuit layout according to claim 1 , further comprising:
a third standard cell abutting to another side of the first standard cell along the first direction and comprising:
two third cell boundaries arranged in parallel in the first direction and extending along the second direction; and
a plurality of third gate lines between the two third cell boundaries and arranged along the first direction, wherein the third gate lines respectively comprise a third gate line width and are distanced from each other by the default gate line pitch, the first gate line width and the third gate line width are different, a third cell width between the two third cell boundaries are integral multiples of the default gate line pitch; and
a dummy gate line between the first standard cell and third standard cell, wherein one of the third cell boundaries and one of the first cell boundaries are overlapped with each other and overlap the dummy gate line.

12 . The integrated circuit layout according to claim 11 , wherein the dummy gate line is divided into two equal portions by the one of the third cell boundaries and the one of the first cell boundaries are overlapped with each other.

13 . The integrated circuit layout according to claim 11 , wherein the first standard cell further comprises a plurality of first active region patterns extending along the first direction and arranged in parallel along the second direction, the third standard cell further comprises a plurality of third active region patterns extending along the first direction and arranged in parallel along the second direction, wherein the first active region patterns and the third active region patterns are aligned along the first direction.

14 . The integrated circuit layout according to claim 13 , wherein the first active region patterns and the third active region patterns have a same width in the second direction.

15 . The integrated circuit layout according to claim 11 , wherein the dummy gate line is aligned to one of the second gate lines or one of the second cell boundaries along the second direction.

16 . The integrated circuit layout according to claim 11 , wherein a dummy gate line width of the dummy gate line equals to the first gate line width or the second gate line width.

17 . The integrated circuit layout according to claim 11 , wherein a dummy gate line width of the dummy gate line is different from the first gate line width or the second gate line width.

18 . The integrated circuit layout according to claim 11 , wherein:
the third gate line width equals to a sum of the first gate line width and a variable; the first gate lines comprise a first gate line space between edges of the first gate lines, the third gate lines comprise a third gate line space between the edges of the third gate lines, wherein the third gate line space is smaller than the first gate line space by the variable; and an edge of the dummy gate line and an edge of the first gate lines adjacent to the edge of the dummy gate lines comprise a first dummy gate line space, another edge of the dummy gate line and an edge of the third gate lines adjacent to the another edge of the dummy gate lines comprise a third dummy gate l

Assignees

• United Microelectronics Corp

Inventors

• Wu Kun-Yuan
• Wang Wei-Jen
• Chen Chien-Fu
• Hsu Chen-Hsien
• Chen Chien-Hung
• Lin Chun-Hsien

Classifications

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06F2119/20

  Design reuse, reusability analysis or reusability optimisation · CPC title

• G06F2117/12

  Sizing, e.g. of transistors or gates · CPC title

• G06F30/39 Primary

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H01L27/0207 Primary

  Electricity · mapped topic