Semiconductor device including abnormality detection circuit and semiconductor device control method for detecting abnormality

Patent metadata

Field	Value
Publication number	US-2022336034-A1
Application number	US-202217573310-A
Country	US
Kind code	A1
Filing date	Jan 11, 2022
Priority date	Apr 16, 2021
Publication date	Oct 20, 2022
Grant date	—

Abstract

A semiconductor device includes a plurality of built-in memories, and each of the built-in memories includes a plurality of memory cells. Each built-in memory includes a selector circuit that connects a selected memory cell among the memory cells to an outside, a memory cell relief circuit that, when a fault has occurred in one of the memory cells, transmits, to the selector circuit, a relief signal configured to connect a normal memory cell to the outside without connecting the one of the memory cells in which the fault has occurred, to the outside, and switches selection in the selector circuit, and an abnormality detection circuit that performs abnormality detection for the memory cell relief circuit, based on a temporal change in the relief signal output from the memory cell relief circuit.

First claim

What is claimed is:

1 . A semiconductor device comprising a plurality of built-in memories, wherein
each of the built-in memories includes: a plurality of memory cells; a selector circuit that connects a selected memory cell among the memory cells to an outside; a memory cell relief circuit that, when a fault has occurred in one of the memory cells, transmits, to the selector circuit, a relief signal configured to connect a normal memory cell to the outside without connecting the one of the memory cells in which the fault has occurred, to the outside, and switches selection in the selector circuit; and an abnormality detection circuit that performs abnormality detection for the memory cell relief circuit, based on a temporal change in the relief signal output from the memory cell relief circuit.

2 . The semiconductor device according to claim 1 , wherein
the abnormality detection circuit includes: a delay circuit that gives a delay to the relief signal output from the memory cell relief circuit to generate a delayed relief signal; and a comparator that compares the relief signal with the delayed relief signal generated by the delay circuit, and detects the temporal change in the relief signal.

3 . The semiconductor device according to claim 2 , wherein the abnormality detection circuit further includes a holding circuit that, when the temporal change in the relief signal is detected by the comparator, continuously holds information on the abnormality detection thereafter.

4 . The semiconductor device according to claim 1 , further comprising an information aggregation circuit that, when an abnormality in the memory cell relief circuit is detected by one abnormality detection circuit in one of the built-in memories, outputs the abnormality as information on an abnormality of the whole built-in memories.

5 . The semiconductor device according to claim 1 , further comprising an output circuit that embeds each piece of the information on the abnormality detection by the abnormality detection circuit provided for each of the built-in memories into one signal in an identifiable manner and outputs the one signal.

6 . A semiconductor device control method for detecting abnormality of a plurality of built-in memories in the semiconductor device, the method comprising:
in each of the built-in memories, connecting a selected memory cell, among a plurality of memory cells in the built-in memory, to an outside through a selector circuit; transmitting, when a fault has occurred in one of the memory cells, a relief signal configured to connect a normal memory cell to the outside without connecting the one of the memory cells in which the fault has occurred to the outside, from a memory cell relief circuit to the selector circuit; and performing abnormality detection for the memory cell relief circuit, based on a temporal change in the relief signal output from the memory cell relief circuit.

Assignees

• Fujitsu Ltd

Inventors

• Yanagida Masahiro
• Fujimoto Hiroyuki

Classifications

• G11C29/38 Primary

  Response verification devices · CPC title

• G11C29/4401 Primary

  for self repair · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title