Memory device

Patent metadata

Field	Value
Publication number	US-2022335996-A1
Application number	US-202217855107-A
Country	US
Kind code	A1
Filing date	Jun 30, 2022
Priority date	Nov 15, 2019
Publication date	Oct 20, 2022
Grant date	—

Abstract

A memory device is provided, the memory device includes multiple cells arranged in a matrix of multiple rows and multiple columns. The memory device further includes multiple bit lines each of which is connected to first cells of the multiple cells arranged in a row of the multiple rows. A voltage control circuit is connectable to a selected bit line of the multiple bit lines and includes a voltage detection circuit that detects an instantaneous supply voltage and a voltage source selection circuit connected to the voltage detection circuit. The voltage source selection circuit selects a voltage source from multiple voltage sources based on the detected instantaneous supply voltage. The voltage source selection circuit includes a switch that connects the selected voltage source to the selected bit line to provide a write voltage.

First claim

What is claimed is:

1 . A memory device, comprising:
a plurality of cells arranged in a matrix comprising a plurality of rows and a plurality of columns; a plurality of bit lines, wherein each of the plurality of bit lines is connected to a first plurality of cells of the plurality of cells arranged in a column of the plurality of columns; and a temperature compensation circuit connectable to a selected bit line of the plurality of bit lines, wherein the temperature compensation circuit comprises:
a reference voltage generator circuit, wherein the reference voltage generator circuit is configured to generate a temperature adjusted reference voltage, and
a voltage regulator circuit connected to the reference voltage generator circuit, wherein the voltage regulator circuit is configured to compare an instantaneous write voltage with the temperature adjusted reference voltage and regulate the instantaneous write voltage based on the comparison.

2 . The memory device of claim 1 , wherein the reference voltage generator circuit comprises:
a first current source; a second current source connected in parallel to the first current source at a reference node; and a variable resistor connected between the reference node and ground, wherein the reference node is configured to provide the temperature adjusted reference voltage.

3 . The memory device of claim 2 , wherein the first current source is a Proportional to Absolute Temperature (PTAT) current source and the second current source is a Zero Temperature Coefficient (ZTC) current source.

4 . The memory device of claim 3 , wherein a first current generated by the PTAT current source is proportional to temperature and increases or decreases in a same direction as the temperature increases or decreases

5 . The memory device of claim 3 , wherein a second current generated by the ZTC current source is invariable relative to temperature.

6 . The memory device of claim 1 , wherein the voltage regulator circuit comprises an amplifier and a third current source, wherein the amplifier comprises a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the amplifier is connected to a reference voltage node, wherein the second input terminal of the amplifier is connected to the selected bit line, and wherein the output terminal of the amplifier is connected to the third current source.

7 . The memory device of claim 6 , wherein the amplifier is configured to regulate an amount of current sinked by the third current source to the selected bit line based on the comparing the instantaneous write voltage with the temperature compensated reference voltage.

8 . The memory device of claim 1 , further comprising a unigain buffer connected between the reference voltage generator and the voltage regulator circuit.

9 . A memory device comprising:
a cell array comprising a plurality of bit lines, each of the plurality of bit lines being connected to a first plurality of cells arranged in a column of the cell array; and a voltage control circuit connectable to a selected bit line of the plurality of bit lines of the cell array, wherein the voltage control circuit is configured to:
detect an instantaneous supply voltage;
compare the instantaneous supply voltage with a reference voltage;
select a voltage source from a plurality of voltage sources based on comparison of the instantaneous supply voltage with the reference voltage; and
connect the selected voltage source to the selected bit line of a cell array, wherein when connected, the selected voltage source provides a write voltage to the selected bit line.

10 . The memory device of claim 9 , wherein voltage control circuit is configured to select a first voltage source of the plurality of voltages sources when the instantaneous supply voltage is less than the reference voltage.

11 . The memory device of claim 9 , wherein voltage control circuit is configured to select a second voltage source of the plurality of voltages sources when the instantaneous supply voltage is more than the reference voltage.

12 . The memory device of claim 9 , wherein the voltage control circuit is configured to compare the instantaneous supply voltage with the reference voltage on expiry of a timer.

13 . The memory device of claim 9 , wherein the voltage control circuit further comprises a latch circuit, wherein the latch circuit is configured to latch a comparison output of the comparator.

14 . The memory device of claim 13 , wherein the latch circuit is triggered by a clock signal, wherein the clock signal is generated by a timer.

15 . A memory device comprising:
a cell array comprising a plurality of bit lines, each of the plurality of bit lines being connected to a first plurality of cells arranged in a column of the cell array; and a temperature compensation circuit connectable to a selected bit line of the plurality of bit lines, wherein the temperature compensation circuit is configured to:
generate a temperature adjusted reference voltage;
detect an instantaneous write voltage;
compare the instantaneous write voltage with the temperature adjusted reference voltage; and
regulate the instantaneous write voltage based on comparing the instantaneous write voltage with the temperature adjusted reference voltage.

16 . The memory device of claim 1 , wherein the temperature compensation circuit comprises:
a first current source; a second current source connected in parallel to the first current source at a reference node; and a variable resistor connected between the reference node and ground, wherein the reference node provides the temperature adjusted reference voltage.

17 . The memory device of claim 16 , wherein the first current source is a Proportional to Absolute Temperature (PTAT) current source and the second current source is a Zero Temperature Coefficient (ZTC) current source.

18 . The memory device of claim 17 , wherein a first current generated by the PTAT current source is proportional to temperature and increases or decreases in a same direction as the temperature increases or decreases.

19 . The memory device of claim 17 , wherein a second current generated by the ZTC current source is invariable relative to temperature.

20 . The memory device of claim 15 , wherein the voltage regulator circuit comprises an amplifier and a third current source, wherein the amplifier comprises a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal of the amplifier is connected to a reference voltage node, wherein the second input terminal of the amplifier is connected to the selected bit line, and wherein the output terminal of the amplifier is connected to the third current source.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lai Chien-An
• Chou Chung-Cheng
• Chih Yu-Der

Classifications

• G11C7/106

  Data output latches · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0038

  Power supply circuits · CPC title

• G11C2013/0071

  Write using write potential applied to access device gate · CPC title