Semiconductor device structure

Patent metadata

Field	Value
Publication number	US-2022335984-A1
Application number	US-202217858986-A
Country	US
Kind code	A1
Filing date	Jul 6, 2022
Priority date	Dec 31, 2019
Publication date	Oct 20, 2022
Grant date	—

Abstract

A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

First claim

What is claimed is:

1 . A method forming a semiconductor device structure comprising:
preparing a semiconductor substrate with an original surface; based on the semiconductor substrate, forming a set of active regions and forming a shallow trench isolation between two active regions of the set of active regions; forming a first interconnection above the shallow trench isolation and between the two active regions, wherein the first interconnection is disposed under the original surface of the semiconductor substrate; forming a second interconnection and a gate region of a transistor, wherein the gate region of the transistor is connected to the second interconnection; and forming a connection plug to electrically connect the first interconnection to a first conductive region of the transistor; wherein the first interconnection is isolated from the semiconductor substrate.

2 . The method of claim 1 , the step of forming the set of active regions and the shallow trench isolation comprising:
depositing a pad-oxide layer and a pad-nitride layer to define the set of active regions; etching the semiconductor substrate outside the active regions to create a trench between the two active regions; and depositing an oxide layer in the trench to form the shallow trench isolation.

3 . The method of claim 1 , the step of forming the first interconnection above the shallow trench isolation comprising:
forming asymmetrical spacers between the two active regions; and form the first interconnection above the shallow trench isolation and between the asymmetrical spacers.

4 . The method of claim 3 , the asymmetrical spacers includes an oxide spacer and a nitride spacer opposite to the oxide spacer.

5 . The method of claim 1 , the step of forming the second interconnection and the gate region of the transistor comprising:
etching the one of the two active regions to create a concave therein; and depositing a high-k insulator layer in the concave and depositing a first conductive material to form the second interconnection and the gate region of the transistor.

6 . The method of claim 3 , wherein the step of forming the connection plug comprising:
etching the one of the two active regions to create a hole and forming a dielectric layer in the hole; removing a portion of the asymmetrical spacers to reveal a sidewall of the first interconnection; depositing a second conductive material in the hole to contact the sidewall of the first interconnection; removing an upper portion of the dielectric layer to reveal the first conductive region of the transistor; and depositing a connection material to connect the first conductive region to the second conductive material; wherein the connection plug comprises the connection material and the second conductive material.

7 . The method of claim 1 , further comprising:
forming a third interconnection to electrically connect a second conductive region of the transistor; wherein the third interconnection is deposited above the original surface of the semiconductor substrate.

8 . The method of claim 1 , wherein the first interconnection is a bit line, and the transistor is an access transistor of a DRAM cell, and the second interconnection is a word line.

9 . A semiconductor device structure comprising:
a semiconductor substrate with an original surface; a transistor comprising a gate structure, a first conductive region, and a second conductive region; a first interconnection under the original surface of the semiconductor substrate and electrically connected to the first conductive region; a second interconnection electrically connected to the gate structure; and a third interconnection above the original surface of the semiconductor substrate and electrically connected to the second conductive region; wherein the first interconnection is isolated from the semiconductor substrate.

10 . The semiconductor device structure of claim 9 , wherein the first interconnection is a bit line, and the transistor is an access transistor of a DRAM cell, the second interconnection is a word line, and the third interconnection is connected to a storage capacitor of the DRAM cell.

11 . The semiconductor device structure of claim 9 , wherein the first interconnection is isolated from the semiconductor substrate by a shallow trench isolation and asymmetrical spacers.

12 . The semiconductor device structure of claim 11 , wherein the shallow trench isolation is under the first interconnection, and sidewalls of the first interconnection are covered by the asymmetrical spacers.

Assignees

• Etron Tech Inc
• Invent And Collaboration Laboratory Pte Ltd

Inventors

• Lu chao-chun
• Huang Li-Ping

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• H01L27/10814

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic