Imaging device, electronic device, and manufacturing method

Patent metadata

Field	Value
Publication number	US-2022328549-A1
Application number	US-202017640086-A
Country	US
Kind code	A1
Filing date	Aug 27, 2020
Priority date	Sep 10, 2019
Publication date	Oct 13, 2022
Grant date	—

Abstract

The present disclosure relates to an imaging device, an electronic device, and a manufacturing method enabling to reduce a manufacturing cost. There are provided: a first semiconductor element including an imaging element configured to generate a pixel signal; and a second semiconductor element in which a first signal processing circuit and a second signal processing circuit that are configured to process the pixel signal are embedded by an embedded member. The first signal processing circuit has a structure including at least one more layer than the second signal processing circuit. There are further provided: a first wiring line that connects the first semiconductor element and the first signal processing circuit; and a second wiring line that connects the first signal processing circuit and the second signal processing circuit. The present disclosure can be applied to an imaging device.

First claim

What is claimed is:

1 . An imaging device comprising:
a first semiconductor element including an imaging element configured to generate a pixel signal; and a second semiconductor element in which a first signal processing circuit and a second signal processing circuit that are configured to process the pixel signal are embedded by an embedded member, wherein the first signal processing circuit has a structure including at least one more layer than the second signal processing circuit.

2 . The imaging device according to claim 1 , further comprising:
a first wiring line that connects the first semiconductor element and the first signal processing circuit.

3 . The imaging device according to claim 2 , further comprising:
a second wiring line that connects the first signal processing circuit and the second signal processing circuit.

4 . The imaging device according to claim 3 , wherein
the first wiring line connects a terminal of the first semiconductor element and a first terminal of the first signal processing circuit, and the second wiring line connects a second terminal of the first signal processing circuit and a third terminal of the second signal processing circuit, the second terminal being different from the first terminal.

5 . The imaging device according to claim 1 , wherein
the layer is an oxide film.

6 . The imaging device according to claim 1 , wherein
a distance between a terminal of the first semiconductor element and a terminal of the first signal processing circuit is shorter than a distance between a terminal of the first semiconductor element and a terminal of the second signal processing circuit.

7 . The imaging device according to claim 1 , wherein
the first signal processing circuit is a memory circuit, and the second signal processing circuit is a logic circuit.

8 . An electronic device including an imaging device comprising:
a first semiconductor element including an imaging element configured to generate a pixel signal; and a second semiconductor element in which a first signal processing circuit and a second signal processing circuit that are configured to process the pixel signal are embedded by an embedded member, wherein the first signal processing circuit has a structure including at least one more layer than the second signal processing circuit.

9 . An imaging device comprising:
a first semiconductor element including an imaging element configured to generate a pixel signal; a second semiconductor element in which a first signal processing circuit and a second signal processing circuit that are configured to process the pixel signal are embedded by an embedded member; and a wiring line that connects the first signal processing circuit and the second signal processing circuit, wherein the wiring line connects a terminal provided in a wiring layer of a lowermost layer of the first signal processing circuit and a terminal provided in a wiring layer of a lowermost layer of the second signal processing circuit.

10 . The imaging device according to claim 9 , wherein
the wiring line is provided along a side surface of the first signal processing circuit and a side surface of the second signal processing circuit.

11 . The imaging device according to claim 10 , wherein
a part of the wiring line is provided along a layer formed on a bonding surface between the first semiconductor element and the second semiconductor element.

12 . The imaging device according to claim 9 , wherein
at least one or more layers are provided between the wiring line and the first signal processing circuit and between the wiring line and the second signal processing circuit.

13 . The imaging device according to claim 12 , wherein
the one or more layers are insulating films.

14 . An electronic device including an imaging device comprising:
a first semiconductor element including an imaging element configured to generate a pixel signal; a second semiconductor element in which a first signal processing circuit and a second signal processing circuit that are configured to process the pixel signal are embedded by an embedded member; and a wiring line that connects the first signal processing circuit and the second signal processing circuit, wherein the wiring line connects a terminal provided in a wiring layer of a lowermost layer of the first signal processing circuit and a terminal provided in a wiring layer of a lowermost layer of the second signal processing circuit.

15 . A manufacturing method for manufacturing an imaging device including:
a first semiconductor element including an imaging element configured to generate a pixel signal on a pixel basis; a second semiconductor element in which a first signal processing circuit and a second signal processing circuit that are configured to process the pixel signal are embedded by an embedded member; and a wiring line that connects the first signal processing circuit and the second signal processing circuit, the manufacturing method comprising: a step of transferring the first signal processing circuit and the second signal processing circuit to the first semiconductor element; a step of forming a first film on the first signal processing circuit and the second signal processing circuit; a step of exposing a part of a first terminal provided in a wiring layer of a lowermost layer of the first signal processing circuit and a part of a second terminal provided in a wiring layer of a lowermost layer of the second signal processing circuit; and a step of forming the wiring line that connects the first terminal and the second terminal.

16 . The manufacturing method according to claim 15 , wherein
a step of, after forming the first film, thinning the first signal processing circuit and the second signal processing circuit.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Nitta Yosuke
• Hagimoto Yoshiya
• Fujii Nobutoshi
• Yamamoto Yuichi

Classifications

• H10W90/00

  Package configurations · CPC title

• H04N25/79

  Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors · CPC title

• H10F39/026

  Wafer-level processing · CPC title

• H10F39/018

  of hybrid image sensors · CPC title

• H01L27/14636

  Electricity · mapped topic