Voltage converter

Patent metadata

Field	Value
Publication number	US-2022321009-A1
Application number	US-202217680022-A
Country	US
Kind code	A1
Filing date	Feb 24, 2022
Priority date	Mar 31, 2021
Publication date	Oct 6, 2022
Grant date	—

Abstract

In an embodiment, a voltage converter is configured to operate by a succession of operating cycles, each cycle comprising an energy accumulation phase and an energy restitution phase, wherein the converter is further configured to determine a duration of one of the phases by comparing a voltage ramp and a first reference voltage, and wherein a slope of the voltage ramp depends on a sign of a current in an inductor at an end of a previous operating cycle.

First claim

What is claimed is:

1 . A voltage converter configured to operate by a succession of operating cycles, each cycle comprising an energy accumulation phase and an energy restitution phase, wherein the converter is configured to:
determine a duration of one of the phases by comparing a voltage ramp and a first reference voltage, wherein a slope of the voltage ramp depends on a sign of a current in an inductor at an end of a previous operating cycle.

2 . The converter according to claim 1 , wherein the one of the phases is the energy restitution phase.

3 . The converter according to claim 2 , wherein the converter is configured to:
increase, from one cycle to a next cycle, the slope of the voltage ramp when the current in the inductor is negative, and lower, from the one cycle to the next cycle, the slope of the voltage ramp when the current in the inductor is positive.

4 . The converter according to claim 1 , wherein the converter comprises a first transistor and a second transistors connected in series between a first node for applying a supply voltage and a second node for applying a second reference voltage, wherein the first and second transistors are connected to each other by a third node, wherein the third node is connected to a fourth output node by the inductor, and wherein the fourth output node is connected to the second node by a first capacitor.

5 . The converter according to claim 4 , wherein the converter comprises a first circuit connected to the third node, the first circuit configured to determine the sign of the current through the inductor.

6 . The converter according to claim 5 ,
wherein the first circuit comprises a third transistor and a fourth transistor connected in series between a fifth node and a sixth node, wherein the third and fourth transistors are connected to each other by a seventh node connected to the third node, wherein the fifth node is connected to the first node by a first resistor and the sixth node is connected to the second node by a second resistor, wherein a control terminal of the third transistor is connected to the second node, wherein a control terminal of the fourth transistor is connected to the first node, wherein a second circuit comprises: an eighth output node configured to provide a first signal that takes a first value when a voltage at the third node is greater than a first supply voltage and a second value when the voltage at the third node is less than the first supply voltage, and a ninth output node configured to provide a second signal that takes a first value when the voltage at the third node is less than the second voltage and a second value when the voltage at the third node is greater than the second voltage.

7 . The converter according to claim 1 , further comprising a second circuit configured to generate the voltage ramp, the slope of the voltage ramp depending on a third signal.

8 . The converter according to claim 7 , wherein the second circuit comprises a circuit of variable capacitance configured to be charged when the voltage ramp is generated, and wherein a capacitance of the circuit depends on a value of the third signal.

9 . The converter according to claim 8 , wherein the third signal has a finite number of possible values, each signal value corresponding to a capacitance value.

10 . The converter according to claim 7 , wherein the converter comprises a third circuit configured to determine a change in the third signal according to values of a first signal and a second signal.

11 . A method for controlling a voltage converter comprising a succession of operating cycles, each cycle comprising an energy accumulation phase and an energy restitution phase, the method comprising:
determining, by the converter, a duration of one of the phases by comparing a voltage ramp and a first reference voltage, wherein a slope of the voltage ramp depends on a sign of a current in an inductor at an end of a previous operating cycle.

12 . The method according to claim 11 , wherein the one of the phases is the energy restitution phase.

13 . The method according to claim 12 , further comprising:
increasing, by the converter, from one cycle to a next cycle, the slope of the voltage ramp when the current in the inductor is negative, and lowering, by the converter, from the one cycle to the next cycle, the slope of the voltage ramp when the current in the inductor is positive.

14 . The method according to claim 11 , wherein the converter comprises a first transistor and a second transistors connected in series between a first node for applying a supply voltage and a second node for applying a second reference voltage, wherein the first and second transistors are connected to each other by a third node, wherein the third node is connected to a fourth output node by the inductor, and wherein the fourth output node is connected to the second node by a first capacitor.

15 . The method according to claim 14 , wherein the converter comprises a first circuit connected to the third node, and wherein the first circuit is configured to determine the sign of the current through the inductor.

16 . The method according to claim 15 ,
wherein the first circuit comprises a third transistor and a fourth transistor connected in series between a fifth node and a sixth node, wherein the third and fourth transistors are connected to each other by a seventh node connected to the third node, wherein the fifth node is connected to the first node by a first resistor and the sixth node is connected to the second node by a second resistor, wherein a control terminal of the third transistor is connected to the second node, wherein a control terminal of the fourth transistor is connected to the first node, and wherein the method comprises: providing, by an eighth output node of a second circuit, a first signal that takes a first value when a voltage at the third node is greater than a first supply voltage and a second value when the voltage at the third node is less than the first supply voltage; and providing, by a ninth output node of the second circuit, a second signal that takes a first value when the voltage at the third node is less than the second voltage and a second value when the voltage at the third node is greater than the second voltage.

17 . The method according to claim 11 , wherein the converter further comprises a second circuit, and wherein the method further comprises:
generating, by the second circuit, the voltage ramp, wherein the slope of the voltage ramp depends on a third signal.

18 . The method according to claim 17 , wherein the second circuit comprises a circuit of variable capacitance, and wherein the method further comprises:
charging the circuit of variable capacitance when the voltage ramp is generated, wherein a capacitance of the circuit of variable capacitance depends on a value of the third signal.

19 . The method according to claim 18 , wherein the third signal has a finite number of possible values, each signal value corresponding to a capacitance value.

20 . The method according to claim 17 , wherein the converter comprises a third circuit, and wherein the method further comprises:
determine a change in the third signal according to values of a first signal and a second signal.

Assignees

• St Microelectronics Rousset

Inventors

• Ortet Sebastien
• Davino Didier
• Collette Remi

Classifications

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/0009

  Devices or circuits for detecting current in a converter · CPC title

• H02M1/0025

  Arrangements for modifying reference values, feedback values or error values in the control loop of a converter · CPC title

• H03K5/2472

  using field effect transistors (H03K5/2436 takes precedence) · CPC title

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title