Clock manager monitoring for time synchronized networks

Patent metadata

Field	Value
Publication number	US-2022303034-A1
Application number	US-202217829042-A
Country	US
Kind code	A1
Filing date	May 31, 2022
Priority date	May 31, 2022
Publication date	Sep 22, 2022
Grant date	—

Abstract

Techniques for clock manager monitoring for time sensitive networks are described. An apparatus, comprises a clock circuitry to manage a clock for a device, a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network, and a detector coupled to the processing circuitry and the clock circuitry, the detector to receive the clock manager control information, generate model control information based on a clock model, compare the clock manager control information with the model control information to generate difference information, and determine whether to generate an alert based on the difference information. Other embodiments are described and claimed.

First claim

What is claimed is:

1 . An apparatus, comprising:
a clock circuitry to manage a clock for a device; a processing circuitry coupled to the clock circuitry, the processing circuitry to execute instructions to perform operations for a clock manager, the clock manager to receive messages with time information for a network and generate clock manager control information to adjust the clock to a network time for the network; and a detector coupled to the processing circuitry and the clock circuitry, the detector to receive the clock manager control information, generate model control information based on a clock model, compare the clock manager control information with the model control information to generate difference information, and determine whether to generate an alert based on the difference information.

2 . The apparatus of claim 1 , wherein the network is a time sensitive network.

3 . The apparatus of claim 1 , wherein the device operates in accordance with an Institute of Electrical and Electronics Engineers (IEEE) 802.1AS and/or 802.1Qbv and/or 802.15.4 standards.

4 . The apparatus of claim 1 , wherein the network time is a precision time protocol (PTP) time.

5 . The apparatus of claim 1 , wherein the messages are synchronization messages or follow up messages for a precision time protocol (PTP).

6 . The apparatus of claim 1 , wherein the clock managed by the clock circuitry is a precision time protocol (PTP) hardware clock (PHC).

7 . The apparatus of claim 1 , wherein the device operates in a clock follower (CF) role.

8 . The apparatus of claim 1 , wherein the clock manager is a precision time protocol (PTP) for Linux (PTP4L) software component configured to account for a time offset between a clock of a clock leader (CL) in a PTP-synchronized network and the clock for the device when operating as a clock follower (CF) in the PTP-synchronized network.

9 . The apparatus of claim 1 , wherein the clock manager control information to comprise a time offset between a reference time and a time maintained by the clock, the reference time based on the time information in at least one message.

10 . The apparatus of claim 1 , wherein the clock manager control information to comprise one or more parameters to adjust the clock circuitry for the device, the one or more parameters to represent adjustments to a phase or frequency of the clock circuitry.

11 . A computing-implemented method, comprising:
receiving messages with time information for a network; generating clock manager control information to adjust a clock to a network time for the network; receiving the clock manager control information; generating model control information based on a clock model; comparing the clock manager control information with the model control information to generate difference information; and determining whether to generate an alert based on the difference information.

12 . The computing-implemented method of claim 11 , wherein the network is a time sensitive network.

13 . The computing-implemented method of claim 11 , wherein the network operates in accordance with an Institute of Electrical and Electronics Engineers (IEEE) 802.1AS and/or 802.1Qbv and/or 802.15.4 standards.

14 . The computing-implemented method of claim 11 , wherein the network time is a precision time protocol (PTP) time.

15 . The computing-implemented method of claim 11 , wherein the messages are synchronization messages or follow up messages for a precision time protocol (PTP).

16 . The computing-implemented method of claim 11 , wherein the clock managed by the clock circuitry is a precision time protocol (PTP) hardware clock (PHC).

17 . The computing-implemented method of claim 11 , wherein the clock manager is a precision time protocol (PTP) for Linux (PTP4L) software component configured to account for a time offset between a clock of a clock leader (CL) in a PTP-synchronized network and the clock for a device when operating as a clock follower (CF) in the PTP-synchronized network.

18 . A non-transitory computer-readable storage device, storing instructions that when executed by processing circuitry of a controller of a time sensitive network (TSN), cause the controller to:
receive messages with time information for a network; generate clock manager control information to adjust a clock to a network time for the network; receive the clock manager control information; generate model control information based on a clock model; compare the clock manager control information with the model control information to generate difference information; and determine whether to generate an alert based on the difference information.

19 . The non-transitory computer-readable storage device of claim 18 , wherein the network is a time sensitive network.

20 . The non-transitory computer-readable storage device of claim 18 , wherein the network operates in accordance with an Institute of Electrical and Electronics Engineers (IEEE) 802.1AS and/or 802.1Qbv and/or 802.15.4 standards.

21 . The non-transitory computer-readable storage device of claim 18 , wherein the network time is a precision time protocol (PTP) time.

22 . The non-transitory computer-readable storage device of claim 18 , wherein the messages are synchronization messages or follow up messages for a precision time protocol (PTP).

23 . The non-transitory computer-readable storage device of claim 18 , wherein the clock managed by the clock circuitry is a precision time protocol (PTP) hardware clock (PHC).

24 . The non-transitory computer-readable storage device of claim 18 , wherein the clock manager is a precision time protocol (PTP) for Linux (PTP4L) software component configured to account for a time offset between a clock of a clock leader (CL) in a PTP-synchronized network and the clock for a device when operating as a clock follower (CF) in the PTP-synchronized network.

25 . The non-transitory computer-readable storage device of claim 18 , wherein the clock manager control information to comprise a time offset between a reference time and a time maintained by the clock, the reference time based on the time information in at least one message.

Assignees

• Intel Corp

Inventors

• Lesi Vuk
• Gutierrez Christopher
• Sastry Manoj
• Juliato Marcio
• Ahmed Shabbir
• Wang Qian

Classifications

• H04J3/067

  Details of the timestamp structure · CPC title

• H04J3/0667 Primary

  Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864) · CPC title

• H04L63/1441

  Countermeasures against malicious traffic (countermeasures against attacks on cryptographic mechanisms H04L9/002) · CPC title

• H04L43/16

  Threshold monitoring · CPC title

• H04L43/106

  using time related information in packets, e.g. by adding timestamps · CPC title