Semiconductor manufacturing method and semiconductor manufacturing apparatus

Patent metadata

Field	Value
Publication number	US-2022301870-A1
Application number	US-202117474929-A
Country	US
Kind code	A1
Filing date	Sep 14, 2021
Priority date	Mar 18, 2021
Publication date	Sep 22, 2022
Grant date	—

Abstract

According to an embodiment, a semiconductor manufacturing method includes forming a first seed layer on an underlying layer with a first gas that is an aminosilane gas. The method further includes forming a first amorphous silicon layer on the first seed layer with a second gas that is a silane gas not containing an amino group. The method further includes forming a second seed layer containing impurities on the first amorphous silicon layer with a third gas that is an aminosilane gas. The method further includes forming a second amorphous silicon layer on the second seed layer with a fourth gas that is a silane gas not containing an amino group.

First claim

1 . A semiconductor manufacturing method comprising:
forming a first seed layer on an underlying layer with a first gas that is an aminosilane gas; forming a first amorphous silicon layer on the first seed layer with a second gas that is a silane gas not containing an amino group; forming a second seed layer containing impurities on the first amorphous silicon layer with a third gas that is an aminosilane gas; and forming a second amorphous silicon layer on the second seed layer with a fourth gas that is a silane gas not containing an amino group.

2 . The method of claim 1 , wherein the impurities contain carbon.

3 . The method of claim 1 , wherein the impurities contain nitrogen.

4 . The method of claim 2 , wherein the impurities contain nitrogen.

5 . The method of claim 1 , wherein the underlying layer is a first insulation layer provided along a sidewall of a through hole that penetrates through a stacked body of a first layer and a second layer provided above a substrate.

6 . The method of claim 2 , wherein the underlying layer is a first insulation layer provided along a sidewall of a through hole that penetrates through a stacked body of a first layer and a second layer provided above a substrate.

7 . The method of claim 3 , wherein the underlying layer is a first insulation layer provided along a sidewall of a through hole that penetrates through a stacked body of a first layer and a second layer provided above a substrate.

8 . The method of claim 5 , further comprising:
forming a second insulation layer on the second amorphous silicon layer to be located at a center of the through hole; forming a silicide layer in upper-end side portions of the first and second amorphous silicon layers; and crystallizing the first and second amorphous silicon layers to a monocrystalline structure using the silicide layer as a catalyst.

9 . The method of claim 8 , wherein the silicide layer is a nickel disilicide layer.

10 . The method of claim 1 , wherein the third gas is same as the first gas.

11 . The method of claim 1 , wherein the third gas is different from the first gas.

12 . The method of claim 1 , wherein the fourth gas is same as the second gas.

13 . The method of claim 1 , wherein the first gas and the third gas are respectively a gas that contains at least one aminosilane selected from a group of butylaminosilane, bis(tert-butylamino)silane, dimethylaminosilane, bis(dimethylamino)silane, tris(dimethylamino)silane, diethylaminosilane, bis(diethylamino)silane, dipropylaminosilane, and diisopropylaminosilane.

14 . The method of claim 1 , wherein the second gas and the fourth gas are respectively a gas that contains at least one silane selected from a group of SiH 2 , SiH 4 , SiH 6 , Si 2 H 4 , Si 2 H 6 , silicon hydride represented by Si m H 2m+2 (where m is a natural number of 3 or more), and silicon hydride represented by Si n H 2n (where n is a natural number of 3 or more).

15 . A semiconductor manufacturing apparatus comprising:
a processing chamber capable of accommodating a plurality of substrates to be processed; a holder arranged in the processing chamber and being capable of holding the substrates to be processed at an interval in a thickness direction; and a gas supply tube arranged in the processing chamber and provided with a plurality of discharge ports that discharge an aminosilane gas towards the substrates to be processed held by the holder, wherein the discharge ports are provided for the respective substrates to be processed in a one-to-one positional relation.

16 . The apparatus of claim 15 , wherein
the processing chamber is provided with an exhaust port for a gas that has processed the substrates to be processed, along the thickness direction, and an cross-sectional area of the exhaust port is larger in a portion close to each of the discharge ports than in a portion far from each of the discharge ports.

17 . The apparatus of claim 15 , wherein a downstream one of the discharge ports in a flow of the aminosilane gas has a larger cross-sectional area than an upstream one of the discharge ports in the flow of the aminosilane gas.

18 . The apparatus of claim 16 , wherein
a downstream one of the discharge ports in a flow of the aminosilane gas has a larger cross-sectional area than an upstream one of the discharge ports in the flow of the aminosilane gas, and a cross-sectional area of the exhaust port is larger in a portion close to the downstream one of the discharge ports in the flow of the aminosilane gas than in a portion close to the upstream one of the discharge ports in the flow of the aminosilane gas.

19 . The apparatus of claim 15 , further comprising a second gas supply tube arranged in the processing chamber and provided with a plurality of second discharge ports that discharge a silane gas not containing an amino group towards the substrates to be processed held by the holder.

20 . The apparatus of claim 19 , further comprising a controller configured to control supply of the aminosilane gas and the silane gas not containing the amino group towards the substrates to be processed, wherein
the controller is configured to control supply of the aminosilane gas to each of the substrates to be processed in such a manner that a first seed layer is formed on an underlying layer provided on that substrate, control supply of the silane gas not containing the amino group to each of the substrates to be processed in such a manner that a first amorphous silicon layer is formed on the first seed layer, control supply of the aminosilane gas to each of the substrates to be processed in such a manner that a second seed layer containing impurities is formed on the first amorphous silicon layer, and control supply of the silane gas not containing the amino group to each of the substrates to be processed in such a manner that a second amorphous silicon layer is formed on the second seed layer.

Assignees

• Kioxia Corp

Inventors

• Fukumoto Atsushi
• Aiso Fumiki

Classifications

• H10P14/3454

  Amorphous · CPC title

• H10P14/3411 Primary

  Silicon, silicon germanium or germanium · CPC title

• H10P14/274 Primary

  using seed materials · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3804 Primary

  using crystallisation-inhibiting elements · CPC title