Vertical transistors with gate connection grid

Patent metadata

Field	Value
Publication number	US-2022285248-A1
Application number	US-202117194846-A
Country	US
Kind code	A1
Filing date	Mar 8, 2021
Priority date	Mar 8, 2021
Publication date	Sep 8, 2022
Grant date	—

Abstract

In a general aspect, a semiconductor device can include a plurality of vertical transistor segments disposed in an active region of a semiconductor region. The plurality of vertical transistor segments can include respective gate electrodes. A first dielectric can be disposed on the active region. An electrically conductive grid can be disposed on the first dielectric. The electrically conductive grid can be electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric. A second dielectric can be disposed on the electrically conductive grid and the first dielectric. A conductive metal layer can be disposed on the second dielectric layer. The conductive metal layer can include a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a vertical transistor including:
a first transistor segment having a first body region, a first source region, and a first gate electrode;
a second transistor segment having a second body region, a second source region, and a second gate electrode;
a first dielectric layer disposed on the vertical transistor; an electrically conductive grid disposed on the first dielectric layer, the electrically conductive grid being electrically coupled with the first gate electrode and the second gate electrode using at least a first conductive contact formed through the first dielectric layer; a second dielectric layer disposed on the electrically conductive grid and the first dielectric layer; and a metal layer disposed on the second dielectric layer, the metal layer including:
a first portion that is electrically coupled with the first body region, the first source region, the second body region, and the second source region using at least a second conductive contact formed through the first dielectric layer and the second dielectric layer; and
a second portion that is electrically coupled with the electrically conductive grid using at least a third conductive contact formed through the second dielectric layer.

2 . The semiconductor device of claim 1 , wherein:
the first gate electrode is one of a first planar-gate electrode or a first trench-gate electrode; and the second gate electrode is one a second planar-gate electrode or a second trench-gate electrode.

3 . The semiconductor device of claim 1 , wherein:
the vertical transistor is included in a semiconductor substrate, the semiconductor substrate being arranged in a plane; and at least a portion of the gate connection grid and a portion of the first segment of the vertical transistor being arranged along a line that is orthogonal to the plane.

4 . The semiconductor device of claim 1 , wherein the metal layer is first metal layer, the semiconductor device further comprising:
a third dielectric layer disposed on the first metal layer and the second dielectric layer; and a second metal layer disposed on the third dielectric layer, the second metal layer including:
a first portion that is electrically coupled with the first portion of the first metal layer through the third dielectric layer; and
a second portion that is electrically coupled with the second portion of the first metal layer through the third dielectric layer.

5 . The semiconductor device of claim 4 , wherein:
the first portion of the second metal layer is disposed on the first portion of the first metal layer; and the second portion of the second metal layer is electrically coupled with the second portion of the first metal layer using at least one conductive via formed through the third dielectric layer.

6 . The semiconductor device of claim 1 , wherein:
the electrically conductive grid and the first conductive contact include tungsten; the first gate electrode and the second gate electrode include doped polysilicon.

7 . The semiconductor device of claim 1 , wherein the vertical transistor is included in a silicon carbide (SiC) semiconductor region.

8 . The semiconductor device of claim 7 , wherein:
the first body region and the second body region are:
of a first conductivity type; and
disposed in the SiC semiconductor region;
the SiC semiconductor region, the first source region and the second source region are of a second conductivity type that is opposite the first conductivity type; the first source region is disposed in the first body region; and the second source region is disposed in the second body region.

9 . The semiconductor device of claim 7 , wherein:
the vertical transistor includes a vertical field-effect transistor (FET), the SiC semiconductor region including:
a drift region of the vertical FET; and
a drain region of the vertical FET.

10 . The semiconductor device of claim 7 , wherein:
the vertical transistor includes a vertical insulated gate bipolar transistor (IGBT), the first source region including a first emitter region of the vertical IGBT, the second source region including a second emitter region of the vertical IGBT, and the SiC semiconductor region including:
a drift region of the vertical IGBT; and
a collector region of the vertical IGBT.

11 . The semiconductor device of claim 1 , wherein:
the first gate electrode is a first portion of a doped polysilicon gate electrode; and the second gate electrode is a second portion the doped polysilicon gate electrode.

12 . The semiconductor device of claim 1 , wherein:
the first gate electrode is a first doped polysilicon gate electrode; and the second gate electrode is a second doped polysilicon gate electrode, the first doped polysilicon gate electrode being electrically coupled with the second doped polysilicon gate electrode via the electrically conductive grid and respective electrical contacts to the electrically conductive grid.

13 . The semiconductor device of claim 1 , wherein:
the at least a first conductive contact formed through the first dielectric layer includes a first plurality of conductive contacts formed through the first dielectric layer; the at least a second conductive contact formed through the first dielectric layer and the second dielectric layer includes a second plurality of conductive contacts formed through the first dielectric layer and the second dielectric layer; and the at least a third conductive contact formed through the second dielectric layer includes a third plurality of conductive contacts formed through the second dielectric layer.

14 . A semiconductor device comprising:
a semiconductor region; an active region disposed in the semiconductor region; an isolation region disposed in the semiconductor region, the isolation region at least partially surrounding the active region; a plurality of vertical transistor segments disposed in the active region, the plurality of vertical transistor segments including respective gate electrodes; a first dielectric layer disposed on the active region; an electrically conductive grid disposed on the first dielectric layer, the electrically conductive grid being electrically coupled with the respective gate electrodes using a plurality of conductive contacts formed through the first dielectric layer; a second dielectric layer disposed on the electrically conductive grid and the first dielectric layer; and a metal layer disposed on the second dielectric layer, the metal layer including a portion that is electrically coupled with the respective gate electrodes through the electrically conductive grid using at least one conductive contact to the electrically conductive grid formed through the second dielectric layer.

15 . The semiconductor device of claim 14 , wherein the metal layer is a first metal layer, the semiconductor device further comprising:
a third dielectric layer disposed on the first metal layer and the second dielectric layer; and a second metal layer including a portion that is electrically coupled with the portion of the first metal layer through the third dielectric layer.

16 . The semiconductor device of claim 14 , wherein the respective gate electrodes include respective planar-gate electrodes or respective trench-gate electrodes.

17 . The semiconductor device of claim 14 , wherein the gate connection grid does not reduce an active area of the active region.

18 . The semiconductor device of claim 14 ,

Assignees

• Semiconductor Components Ind Llc

Inventors

• Neyer Thomas
• De Vleeschouwer Herbert
• Allerstam Fredrik

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H10W20/484 Primary

  Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D64/252

  for vertical or pseudo-vertical devices · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title