Sidewall wetting barrier for conductive pillars

Patent metadata

Field	Value
Publication number	US-2022270995-A1
Application number	US-202117185244-A
Country	US
Kind code	A1
Filing date	Feb 25, 2021
Priority date	Feb 25, 2021
Publication date	Aug 25, 2022
Grant date	—

Abstract

Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems.

First claim

A complete listing of the claims, including current amendments (if any), is as follows:

1 . An integrated circuit (IC) structure, comprising:
a die; a pillar on the die, a first surface of the pillar facing the die; a wetting barrier on a second surface of the pillar, a width of the wetting barrier being greater than a width of the pillar; and a solder cap on the wetting barrier such that the die is electrically coupled to the solder cap at least through the pillar and the wetting barrier, wherein the pillar and the wetting barrier are formed from a same conductive material.

2 . The IC structure of claim 1 , further comprising:
a low wetting layer on at least a portion of a surface of the wetting barrier not covered by the pillar.

3 . The IC structure of claim 2 , wherein the low wetting layer has a lower solderability than the pillar.

4 . The IC structure of claim 2 , wherein the low wetting layer is formed from any combination of nickel (Ni), aluminum (Al), and chromium (Cr).

5 . The IC structure of claim 2 , wherein the low wetting layer is formed in between the wetting barrier and the solder cap.

6 . The IC structure of claim 5 ,
wherein the pillar is a first pillar, and wherein the IC structure further comprises:
a second pillar on the low wetting layer; and
a contact layer in between the second pillar and the solder cap.

7 . The IC structure of claim 6 , wherein the contact layer is formed from nickel (Ni).

8 . The IC structure of claim 2 , further comprising:
a contact layer in between the wetting barrier and the solder cap.

9 . The IC structure of claim 8 , wherein the contact layer is formed from nickel (Ni).

10 . The IC structure of claim 1 , wherein the width of the wetting barrier is greater than a width of the solder cap.

11 . (canceled)

12 . The IC structure of claim 1 , wherein the pillar and the wetting barrier are formed from copper (Cu).

13 . (canceled)

14 . (canceled)

15 . The IC structure of claim 1 , wherein the IC structure is incorporated into an apparatus selected from the group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, an Internet of things (IoT) device, a laptop computer, a server, and a device in an automotive vehicle.

16 . A method of fabricating an integrated circuit (IC) structure, the method comprising:
forming a pillar on a die, a first surface of the pillar facing the die; forming a wetting barrier on a second surface of the pillar, a width of the wetting barrier being greater than a width of the pillar; and forming a solder cap on the wetting barrier such that the die is electrically coupled to the solder cap at least through the pillar and the wetting barrier, wherein the pillar and the wetting barrier are formed from a same conductive material.

17 . The method of claim 16 , wherein forming the pillar and forming the wetting barrier comprise:
depositing a first photoresist on the die; patterning the first photoresist with a first opening; forming the pillar in the first opening such that the second surface of the pillar is exposed at a top surface of the first photoresist; and forming the wetting barrier on the exposed second surface of the pillar with the first photoresist in place.

18 . The method of claim 17 ,
wherein the pillar is formed by plating copper (Cu) in the first opening, or wherein the wetting barrier is formed by plating Cu on the pillar, or both.

19 . The method of claim 17 , wherein forming the solder cap comprises:
depositing a second photoresist on the first photoresist to cover the wetting barrier; patterning the second photoresist with a second opening to expose a portion the wetting barrier, a width of the second opening being less than a width of the first opening; depositing a solder material on the exposed portion of the wetting barrier within the second opening; removing the first and second photoresists subsequent to depositing the solder material; and performing a seed layer etch and a solder reflow subsequent to removing the first and second photoresists.

20 . The method of claim 19 , wherein forming the solder cap further comprises:
performing a plasma treatment of the wetting barrier subsequent to removing the first and second photoresists and prior to performing the seed layer etch and the solder reflow.

21 . The method of claim 17 , further comprising:
forming a low wetting layer on at least a portion of a surface of the wetting barrier not covered by the pillar, wherein the low wetting layer has a lower solderability than the pillar.

22 . The method of claim 21 , wherein the low wetting layer is formed from any combination of nickel (Ni), aluminum (Al), and chromium (Cr).

23 . The method of claim 21 ,
wherein forming the low wetting layer comprises:
forming the low wetting layer on the wetting barrier with the first photoresist still in place, and
wherein forming the solder cap comprises:
depositing a second photoresist on the first photoresist to cover the low wetting layer;
patterning the second photoresist with a second opening to expose a portion of the surface of the low wetting layer, a width of the second opening being less than a width of the first opening;
depositing a solder material on the exposed portion of the low wetting layer within the second opening;
removing the first and second photoresists subsequent to depositing the solder material; and
performing a seed layer etch and a solder reflow subsequent to removing the first and second photoresists.

24 . The method of claim 23 , wherein forming the solder cap further comprises:
performing a plasma treatment of the wetting barrier subsequent to removing the first and second photoresists and prior to performing the seed layer etch and the solder reflow.

25 . The method of claim 17 , further comprising:
forming a contact layer on the wetting barrier such that the contact layer is in between the wetting barrier and the solder cap.

26 . The method of claim 25 ,
wherein forming the contact layer comprises:
depositing a second photoresist on the first photoresist to cover the low wetting layer;
patterning the second photoresist with a second opening to expose a portion of the surface of the low wetting layer, a width of the second opening being less than a width of the first opening;
etching the exposed portion of the low wetting layer to expose a portion of the wetting barrier; and
forming the contact layer on the exposed portion of the wetting barrier, and
wherein forming the solder cap comprises:
depositing a solder material on the contact layer within the second opening;
removing the first and second photoresists subsequent to depositing the solder material; and
performing a seed layer etch and a solder reflow subsequent to removing the first and second photoresists.

27 . The method of claim 26 , wherein the contact layer is formed by plating nickel (Ni) on the exposed portion of the wetting barrier.

28 . The method of claim 25 ,
wherein the pillar is a first pillar, wherein forming the contact layer comprises:
depositing a second photoresist on the first pho

Assignees

• Qualcomm Inc

Inventors

• Hu Wei
• He Dongming
• Yin Wen
• Guan Zhe
• Zhao Lily

Classifications

• H10W72/01257

  by reflowing · CPC title

• H10W72/01255

  by using masks · CPC title

• H10W72/01208

  using permanent auxiliary members, e.g. using solder flow barriers, spacers or alignment marks · CPC title

• H10W72/255

  of outermost layers of multilayered bumps, e.g. material of a coating · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title