Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

Patent metadata

Field	Value
Publication number	US-2022261151-A1
Application number	US-202217662100-A
Country	US
Kind code	A1
Filing date	May 5, 2022
Priority date	Jan 11, 2016
Publication date	Aug 18, 2022
Grant date	—

Abstract

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

First claim

What is claimed is:

1 . An apparatus comprising:
a controller configured to receive a plurality of memory access commands and to determine a respective partition of a plurality of partitions for each of the plurality of memory access commands, the controller further configured to provide each of the plurality of memory access commands to a local controller of a plurality of local controllers associated with the respective partition, wherein the controller comprises: a command and address interface circuit configured to receive the plurality of memory access commands and associated address information from an external command and address bus; and a command block coupled to the command and address bus and configured to determine a memory access command type and a respective target partition of the plurality of partitions for each of the plurality of memory access commands, and configured to provide each of the plurality of memory access commands to a respective local controller associated with the target partition based on a separation timing rule, wherein the separation timing rule for each of the plurality of memory access commands is based on the memory access command type, the target partition associated with the memory access command, and a memory access command type and a target partition associated with another memory access command immediately preceding the memory access command.

2 . The apparatus of claim 1 , further comprising a memory array including the plurality of partitions.

3 . The apparatus of claim 2 , wherein each of the plurality of partitions comprises a respective plurality of memory cells.

4 . The apparatus of claim 1 , further comprising the plurality of local controllers, wherein each of the plurality of local controllers is configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of the plurality of memory access commands responsive to receiving the respective memory access command from the controller.

5 . The apparatus of claim 4 , further comprising a plurality of data buffers, each coupled to a respective partition of the plurality of partitions and coupled to a respective local controller of the plurality of local controllers to independently and concurrently receive data fr©m or provide data to the respective one of the plurality of partitions.

6 . The apparatus of claim 4 , wherein a local controller of the plurality of local controllers comprises:
a driver configured to drive voltages along access lines; and a sequencer configured to execute an algorithm associated with the respective memory access command of the plurality of memory access commands.

7 . The apparatus of claim 6 , wherein the driver and sequencer are configured to:
write data from the data. buffer associated with the local controller to the respective partition of the plurality of partitions associated with the local controller; or read data from the respective partition of the plurality of partitions associated with the local controller and latch the read data at a data buffer associated with the local controller.

8 . The apparatus of claim 6 , wherein the local controller of the plurality of local controllers further comprises sense amplifiers configured to sense data during execution of a respective memory access command of the plurality of memory access commands.

9 . The apparatus of claim 1 , wherein the separation timing rule including a first separating timing rule associated with a first memory access command of a first type followed by a second memory access command of a second type, and a second separating timing rule associated with a third memory access command of the second type followed by a third memory access command of the first type, wherein the first separation timing rule is different from the second separation timing rule.

10 . An apparatus comprising:
a controller configured to provide memory access commands to a non-volatile memory according to separation timing rules for the memory access commands, wherein the controller is configured to:
provide a first memory access command of a first type to a first partition of a plurality of partitions via a respective local controller associated with the first partition;
responsive to receiving a second memory access command of the first type to the first partition of the plurality of partitions, provide the second memory access command a minimum of a first time after the first memory access command to the first partition via the respective local controller associated with the first partition; and
responsive to receiving a third memory access command of the first type to a second partition of the plurality of partitions, provide the third memory access command a minimum of a second time after the first memory access command to the second partition via a respective local controller associated with the second partition, wherein the second time is different from the first time.

11 . The apparatus of claim 10 , wherein the controller is further configured to control a first data buffer associated with the first partition to execute memory access to the first partition based on the first memory access command.

12 . The apparatus of claim 10 , wherein responsive to receiving the second memory access command of the first type to the first partition of the plurality of partitions, the controller is further configured to control the first data buffer to execute memory access to the first partition based on the second memory access command.

13 . The apparatus of claim 10 , wherein responsive to receiving the third memory access command of the first type to a second partition of the plurality of partitions, the controller is further configured to control a second data buffer associated with the second partition to execute memory access to the second partition based on the third memory access command.

14 . The apparatus of claim 10 , wherein the controller is further configured to:
responsive to receiving a fourth memory access command of a second type to the first partition of the plurality of partitions, provide the fourth memory access command a minimum of a third time after the first memory access command to the first partition via the local controller associated with the first partition, wherein the third time is different from the first time.

15 . The apparatus of claim 14 , wherein the first memory access command of the first type comprises a read memory access command and the fourth memory access command of the second type comprises a write memory access command.

16 . The apparatus of claim 10 , further comprising the non-volatile memory, the non-volatile memory comprising the plurality of partitions and a plurality of local controllers, wherein each of the plurality of local controllers is configured to independently and concurrently control a respective data buffer associated with a respective one of the plurality of partitions, wherein each of the plurality of partitions comprises a respective plurality of memory cells.

17 . A method comprising:
receiving a first memory access command and a second memory access command at a controller of a memory; providing the first memory access command to a first local controller of the memory coupled to a first target partition; prior to providing the second memory access command to a second local controller, determining whether a separation timing rule is met, wherein the separation timing rule is based on a memory command type of the first memory access c

Assignees

• Micron Technology Inc

Inventors

• Sundaram Rajesh
• Kau Derchang
• Jungroth Owen W
• Chu Daniel
• Zeng Raymond W
• Qawami Shekoufeh

Classifications

• G06F3/0656

  Data buffering arrangements · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G11C8/12

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title