Ceramic electronic device and manufacturing method of ceramic electronic device

Patent metadata

Field	Value
Publication number	US-2022246355-A1
Application number	US-202217584964-A
Country	US
Kind code	A1
Filing date	Jan 26, 2022
Priority date	Feb 3, 2021
Publication date	Aug 4, 2022
Grant date	—

Abstract

A ceramic electronic device includes a multilayer chip including a multilayer structure, a first cover layer and a second cover layer and having a parallelepiped shape, the multilayer structure having a structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and are alternately exposed to a first end face and a second end face of the multilayer chip, the first end face being opposite to the second end face, the first cover layer being provided on an upper face of the multilayer structure in a stacking direction, the second cover layer being provided on a lower face of the multilayer structure, a first external electrode formed on the first end face, and a second external electrode formed on the second end face. In this structure, a relationship of 0.20≤R1/√{square root over ( )}(P1 2 −C1 2 )≤0.80 is satisfied.

First claim

What is claimed is:

1 . A ceramic electronic device comprising:
a multilayer chip comprising a multilayer structure, a first cover layer and a second cover layer and having a parallelepiped shape, the multilayer structure having a structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and are alternately exposed to a first end face and a second end face of the multilayer chip, the first end face being opposite to the second end face, the first cover layer being provided on an upper face of the multilayer structure in a stacking direction, the second cover layer being provided on a lower face of the multilayer structure; a first external electrode formed on the first end face; and a second external electrode formed on the second end face, wherein a relationship of 0.20≤R1/√{square root over ( )}(P1 2 −C1 2 )≤0.80 is satisfied when a direction in which the first end face is opposite to the second end face is an X-axis direction, the stacking direction is a Z-axis direction, and a direction vertical to the X-axis direction and the Z-axis direction is a Y-axis direction, a curvature radius of a corner portion of the first cover layer on a side of the first external electrode in a cross section in a XZ-plane passing through a center in the Y-axis direction of the multilayer chip is a curvature radius R1, a straight line obtained by connecting edges of internal electrode layers on s side of the first external electrode not connected to the first external electrode is a straight line L, an intersection of the straight line L and an internal electrode layer that is closest to the first cover layer is an intersection point N1, a straight line drawn in the X-axis direction so as to contact an upper face of the multilayer chip is a straight line M, a straight line drawn in the Z-axis direction so as to contact the first end face is a straight line N, an intersection point of the straight line M and the straight line N is an intersection point O, a minimum distance between the intersection point N1 and the straight line M is a distance C1 and a minimum distance between the intersection point N1 and the intersection point O is a distance P1.

2 . The ceramic electronic device as claimed in claim 1 , wherein the curvature radius R1, the distance C1 and the distance P1 satisfy a relationship of 0.25≤R1/√{square root over ( )}(P1 2 −C1 2 )≤0.75.

3 . The ceramic electronic device as claimed in claim 1 ,
wherein a surface of the first external electrode has no inflection point, wherein a plated layer is provided on the surface of the first external electrode.

4 . The ceramic electronic device as claimed in claim 1 ,
wherein the curvature radius R1 is 1% or more and 15% or less of a longitudinal size of the multilayer chip.

5 . The ceramic electronic device as claimed in claim 1 ,
wherein the distance C1 is 3% or more and 35% or less of a size of the multilayer chip in a height direction.

6 . The ceramic electronic device as claimed in claim 1 ,
Wherein the distance P1 is 10% or more and 45% or less of a size of the multilayer chip in a height direction.

7 . A manufacturing method of a ceramic electronic device comprising:
forming a ceramic multilayer structure having a parallelepiped shape, by stacking a plurality of pattern-formed sheets in each of which a conductive paste for forming internal electrode layers is printed on a dielectric green sheet including ceramic, each of a plurality of conductive pastes for forming internal electrode layers being alternately exposed to a first end face and a second end face of the ceramic multilayer structure, and by providing a first cover sheet including ceramic on an upper face of the ceramic multilayer structure in a stacking direction of the ceramic multilayer structure and providing a second cover sheet including ceramic on a lower face of the ceramic multilayer structure; polishing corner portions of the ceramic multilayer structure; painting a first conductive paste for forming the first external electrode on the first end face; painting a second conductive paste for forming the second external electrode on the second end face; forming a dielectric layer from the dielectric green sheet, an internal electrode layer from the conductive paste for forming internal electrode layers, a first cover layer from the first cover sheet, a second cover layer from the second cover sheet, a first external electrode from the first conductive paste for forming the first external electrode, and a second external electrode from the second conductive paste for forming the second external electrode by firing the ceramic multilayer structure, the first conductive paste for forming the first external electrode and the second conductive paste for forming the second external electrode, wherein the corner portions of the ceramic multilayer structure are polished so that a relationship of 0.20≤R1/√{square root over ( )}(P1 2 −C1 2 )≤0.80 is satisfied when a direction in which the first end face is opposite to the second end face is an X-axis direction, a stacking direction is a Z-axis direction, and a direction vertical to the X-axis direction and the Z-axis direction is a Y-axis direction, a curvature radius of a corner portion of the first cover layer on a side of the first external electrode in a cross section in a XZ-plane passing through a center in the Y-axis direction of a multilayer chip formed from the ceramic multilayer structure is a curvature radius R1, a straight line obtained by connecting edges of internal electrode layers on s side of the first external electrode not connected to the first external electrode is a straight line L, an intersection of the straight line L and an internal electrode layer that is closest to the first cover layer is an intersection point N1, a straight line drawn in the X-axis direction so as to contact an upper face of the multilayer chip is a straight line M, a straight line drawn in the Z-axis direction so as to contact the first end face is a straight line N, an intersection point of the straight line M and the straight line N is an intersection point O, a minimum distance between the intersection point N1 and the straight line M is a distance C1 and a minimum distance between the intersection point N1 and the intersection point O is a distance P1.

Assignees

• Taiyo Yuden Kk

Inventors

• Tahara Mikio

Classifications

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/2325

  characterised by the material of the terminals · CPC title

• H01G4/228

  Terminals · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title

• H01G4/248 Primary

  the terminals embracing or surrounding the capacitive element, e.g. caps (H01G4/252 takes precedence) · CPC title