High voltage device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2022223464-A1
Application number	US-202117547829-A
Country	US
Kind code	A1
Filing date	Dec 10, 2021
Priority date	Jan 12, 2021
Publication date	Jul 14, 2022
Grant date	—

Abstract

A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

First claim

What is claimed is:

1 . A high voltage device, comprising:
a semiconductor layer, which is formed on a substrate; a well, which has a first conductivity type, and is formed in the semiconductor layer; a bulk region, which has a second conductivity type, and is formed in the semiconductor layer, wherein the bulk region is in contact with the well along a channel direction; a gate, which is formed on the semiconductor layer, wherein a portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in an ON operation; and a source having the first conductivity type and a drain having the first conductivity type, wherein the source and the drain are formed below and in contact with a top surface of the semiconductor layer, wherein the source and the drain are at two different sides of the gate, respectively, wherein the source is in the bulk region, whereas, the drain is in a part of the well which is away from the bulk region, wherein a portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain; wherein a first concentration peak region of the bulk region is vertically below and in contact with the source; wherein a concentration of the second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

2 . The high voltage device of claim 1 , wherein a second concentration peak region of the bulk region is vertically below and in contact with the top surface of the semiconductor layer, wherein the second concentration peak region encompasses and is in contact with the source, and wherein the concentration of the second conductivity type impurities of the second concentration peak region is higher than that of other regions excluding the first concentration peak region in the bulk region.

3 . The high voltage device of claim 1 , wherein the bulk region further includes: a first layer, which is formed via a first process step, wherein at the same time, the first process step forms another first layer in another device in the semiconductor layer, and wherein a depth of the first layer extending downward from the top surface is greater than that of the source.

4 . The high voltage device of claim 3 , wherein the bulk region further includes: a second layer, which is formed via a second process step, wherein at the same time, the second process step forms another second layer in the another device in the semiconductor layer, and wherein a depth of the second layer extending downward from the top surface is greater than that of the first layer.

5 . The high voltage device of claim 1 , further comprising:
a buried layer, wherein at least a portion of the buried layer is formed in the semiconductor layer, wherein the buried layer has the first conductivity type, and wherein the buried layer is vertically below the bulk region and the well.

6 . The high voltage device of claim 1 , further comprising:
a drift oxide region, which is formed on the semiconductor layer, wherein the gate is vertically above and in contact with the drift oxide region.

7 . The high voltage device of claim 6 , wherein the drift oxide region includes a local oxidation of silicon (LOCOS) structure, a shallow trench isolation (STI) structure, or a chemical vapor deposition (CVD) oxide structure.

8 . The high voltage device of claim 2 , wherein a depth of the source extending downward from the top surface is greater than that of the second concentration peak region.

9 . The high voltage device of claim 1 , wherein the semiconductor layer is a P-type epitaxial silicon layer with a resistance 45 Ohm-cm.

10 . The high voltage device of claim 7 , wherein the drift oxide region includes the CVD oxide region with a thickness of 400 Å-450 Å.

11 . The high voltage device of claim 1 , wherein the high voltage device is a laterally diffused metal oxide semiconductor (LDMOS) device with a gate driving voltage of 3.3V and a gate oxide thickness of 80 Å-100 Å.

12 . The high voltage device of claim 11 , wherein a low voltage device is formed on the substrate, and the low voltage device has a channel length of 0.18 μm.

13 . The high voltage device of claim 1 , wherein the first concentration peak region is formed by a self-aligned process step, wherein the self-aligned process step includes: etching a poly silicon layer to form a conductive layer of the gate; and using the conductive layer as a mask and forming the first concentration peak region by an ion implantation step.

14 . A manufacturing method of a high voltage device, comprising:
forming a semiconductor layer on a substrate; forming a well in the semiconductor layer, wherein the well has a first conductivity type; forming a bulk region in the semiconductor layer, wherein the bulk region has a second conductivity type, wherein the bulk region is in contact with the well along a channel direction; forming a gate on the semiconductor layer, wherein a portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in an ON operation; and forming a source and a drain below a top surface of the semiconductor layer and causing the source and the drain to be in contact with the top surface of the semiconductor layer, wherein both the source and the drain have the first conductivity type, wherein the source and the drain are at two different sides of the gate, respectively, wherein the source is in the bulk region, whereas, the drain is in a part of the well which is away from the bulk region, wherein a portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain; wherein a first concentration peak region of the bulk region is vertically below and in contact with the source; wherein a concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

15 . The manufacturing method of the high voltage device of claim 14 , wherein a second concentration peak region of the bulk region is vertically below and in contact with the top surface of the semiconductor layer, wherein the second concentration peak region encompasses and is in contact with the source, and wherein the concentration of the second conductivity type impurities of the second concentration peak region is higher than that of other regions excluding the first concentration peak region in the bulk region.

16 . The manufacturing method of the high voltage device of claim 14 , wherein the bulk region further includes: a first layer, which is formed via a first process step, wherein at the same time, the first process step forms another first layer in another device in the semiconductor layer, and wherein a depth of the first layer extending downward from the top surface is greater than that of the source.

17 . The manufacturing method of the high voltage device of claim 16 , wherein the bulk region further includes: a second layer, which is formed via a second process step, wherein at the same time, the second process step forms another second layer in the another device in the semiconductor layer, and wherein a depth of the second layer extending downward from the top surface is greater than that of the first layer.

18 . The manufacturing method of the high voltage device of claim 14 , further comprising:
forming a buri

Assignees

• Richtek Technology Corp

Inventors

• Yu Kun-Huang
• Chen Chien-Yu
• Liao Ting-Wei
• Hsiung Chih-Wen
• Chang Chun-Lung
• Chiu Kuo-Chin
• Weng Wu-Te
• Chiu Chien-Wei
• Hu Yong-Zhong
• Yang Ta-Yung

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/0128

  comprising multiple local oxidation process steps · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/012

  using local oxidation of silicon [LOCOS] · CPC title

• H10P90/1906

  Preparing SOI wafers · CPC title