Semiconductor device

Patent metadata

Field	Value
Publication number	US-2022216349-A1
Application number	US-202217701930-A
Country	US
Kind code	A1
Filing date	Mar 23, 2022
Priority date	Dec 3, 2015
Publication date	Jul 7, 2022
Grant date	—

Abstract

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
first to third multi-bridge channel structures arranged in a second direction and sequentially spaced apart from one another in a first direction that is substantially perpendicular to the second direction; a first gate structure arranged in the first direction, the first gate structure surrounding the first multi-bridge channel structure; a first source and drain region located in the first multi-bridge channel structure on respective sides of the first gate structure; a second gate structure arranged in the first direction and spaced apart from the first gate structure in the first direction, the second gate structure surrounding the second and third multi-bridge channel structures; second and third source and drain regions located in the second and third multi-bridge channel structures on respective sides of the second gate structure; a third gate structure spaced apart from the second gate structure in the second direction and spaced apart from the first gate structure in the first direction, the third gate structure surrounding the third multi-bridge channel structure; a fourth source and drain region located in the third multi-bridge channel structure on respective sides of the third gate structure; wherein the first to third multi-bridge channel structures are surrounded with the first to third gate structures, respectively, and each of the first to third multi-bridge channel structures comprises a plurality of nano-bridges serving as channels, the plurality of nano-bridges stacked apart from one another in a third direction that is substantially perpendicular to a plane defined by the first direction and the second direction, and at least one of the first to third multi-bridge channel structures respectively surrounded by the first to third gate structures comprises a different number of nano-bridges from the other multi-bridge channel structures.

2 . The semiconductor device of claim 1 , wherein the lowermost nano-bridges in the first to third multi-bridge channel structures are disposed at the same height in the third direction from the plane defined by the first direction and the second direction.

3 . The semiconductor device of claim 1 , wherein the uppermost nano-bridges in the first to third multi-bridge channel structures are disposed at the different height in the third direction from the plane defined by the first direction and the second direction.

4 . The semiconductor device of claim 1 , wherein the plurality of nano-bridges bridges in each of the first to third multi-bridge channel structures are stacked apart from one another at the same interval in the third direction.

5 . The semiconductor device of claim 1 , wherein each of the plurality of nano-bridges bridges in the first to third multi-bridge channel structures is formed of a nano-sheet, and wherein a length of the nano-sheet in the second direction is greater than a length of the nano-sheet in the first direction.

6 . The semiconductor device of claim 5 , wherein the nano-sheet is formed of quadrangular sectional shape or rectangular sectional shape.

7 . The semiconductor device of claim 1 , wherein a number of nano-bridges included in the second multi-bridge channel structure surrounded by the second gate structure is less than a number of nano-bridges included in the first multi-bridge channel structure surrounded by the first gate structure.

8 . The semiconductor device of claim 1 , wherein a number of nano-bridges included in the first multi-bridge channel structure surrounded by the first gate structure is less than a number of nano-bridges included in the third multi-bridge channel structure surrounded by the second gate structure.

9 . The semiconductor device of claim 1 , wherein a number of nano-bridges included in the second multi-bridge channel structure surrounded by the second gate structure is less than a number of nano-bridges included in the third multi-bridge channel structure surrounded by the third gate structure.

10 . The semiconductor device of claim 1 , wherein a number of nano-bridges included in the second multi-bridge channel structure surrounded by the second gate structure is less than a number of nano-bridges included in the third multi-bridge channel structure surrounded by the second gate structure.

11 . A semiconductor device, comprising:
first to third multi-bridge channel structures arranged in a second direction and sequentially spaced apart from one another in a first direction that is substantially perpendicular to the second direction; a first gate structure arranged in the first direction, the first gate structure surrounding the first multi-bridge channel structure; a first source and drain region located in the first multi-bridge channel structure on respective sides of the first gate structure; a second gate structure arranged in the first direction and spaced apart from the first gate structure in the second direction, the second gate structure surrounding the first and second multi-bridge channel structures; second and third source and drain regions located in the first and second multi-bridge channel structures on respective sides of the second gate structure; a third gate structure spaced apart from the first gate structure in the first direction and spaced apart from the second gate structure in the second direction, the third gate structure surrounding the third multi-bridge channel structure; a fourth source and drain region located in the third multi-bridge channel structure on respective sides of the third gate structure; wherein the first to third multi-bridge channel structures are surrounded with the first to third gate structures, respectively, and each of the first to third multi-bridge channel structures comprises a plurality of nano-bridges serving as channels, the plurality of nano-bridges stacked apart from one another in a third direction that is substantially perpendicular to a plane defined by the first direction and the second direction, and at least one of the first to third multi-bridge channel structures respectively surrounded by the first to third gate structures comprises a different number of nano-bridges from the other multi-bridge channel structures.

12 . The semiconductor device of claim 11 , wherein the lowermost nano-bridges in the first to third multi-bridge channel structures are disposed at the same height in the third direction from the plane defined by the first direction and the second direction.

13 . The semiconductor device of claim 11 , wherein the uppermost nano-bridges in the first to third multi-bridge channel structures are disposed at the different height in the third direction from the plane defined by the first direction and the second direction.

14 . The semiconductor device of claim 11 , wherein the plurality of nano-bridges bridges in each of the first to third multi-bridge channel structures are stacked apart from one another at the same interval in the third direction.

15 . The semiconductor device of claim 11 , wherein each of the plurality of nano-bridges bridges in the first to third multi-bridge channel structures is formed of a nano-sheet, and wherein a length of the nano-sheet in the second direction is greater than a length of the nano-sheet in the first direction.

16 . The semiconductor device of claim 15 , wherein the nano-sheet is formed of quadrangular sectional shape or rectangular sectional shape.

17 . The semiconductor device of claim 11 , wherein a number of nano-bridges included in the secon

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dong-Hun
• Kim Dong-Won

Classifications

• H10P14/3464

  Nanotubes · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10D84/8311

  the IGFETs characterised by having different channel structures · CPC title

• H10D62/292

  Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title