Semiconductor device having multiple electrostatic discharge (esd) paths

Patent metadata

Field	Value
Publication number	US-2022208752-A1
Application number	US-202217699471-A
Country	US
Kind code	A1
Filing date	Mar 21, 2022
Priority date	Sep 18, 2019
Publication date	Jun 30, 2022
Grant date	—

Abstract

A semiconductor device includes a first diode, a second diode, a clamp circuit and a third diode. The first diode is coupled between an input/output (I/O) pad and a first voltage terminal. The second diode is coupled with the first diode, the I/O pad and a second voltage terminal. The clamp circuit is coupled between the first voltage terminal and the second voltage terminal. The second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal. The third diode, coupled to the first voltage terminal, and the second diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first diode, wherein a first terminal of the first diode is coupled to a first voltage terminal that is configured to receive a first supply voltage; a second diode, wherein a first terminal of the second diode, an input/output (I/O) pad, and a second terminal of the first diode are coupled to each other, and a second terminal of the second diode is coupled to a second voltage terminal that is configured to receive a second supply voltage; a clamp circuit coupled between the first voltage terminal and the second voltage terminal, wherein the second diode and the clamp circuit are configured to direct a first part of an electrostatic discharge (ESD) current flowing between the I/O pad and the first voltage terminal; and a third diode, wherein a first terminal and a second terminal of the third diode are coupled to the first voltage terminal; wherein the second diode and the third diode include a first semiconductor structure configured to direct a second part of the ESD current flowing between the I/O pad and the first voltage terminal.

2 . The semiconductor device of claim 1 , wherein the first semiconductor structure in the second diode and the third diode is configured to operate as an equivalent silicon controlled rectifier (SCR) circuit.

3 . The semiconductor device of claim 1 , wherein the first semiconductor structure in the second diode and the third diode comprises:
a substrate; a first well of a first type disposed on the substrate; a first doped region of the first type disposed in the first well and configured as the second terminal of the second diode; a second doped region of a second type disposed in the first well and configured as the first terminal of the second diode; a second well of the second type disposed on the substrate and adjacent to the first well; a third doped region of the first type disposed in the second well and configured as the first terminal of the third diode; and a fourth doped region of the second type disposed in the second well and configured as the second terminal of the third diode; wherein the second doped region, the first well, the substrate, the second well, and the third doped region are configured to operate as an equivalent silicon controlled rectifier (SCR) circuit.

4 . The semiconductor device of claim 1 , further comprising:
at least one of a fourth diode coupled to the first diode in parallel between the I/O pad and the first voltage terminal, a fifth diode coupled to the second diode in parallel between the I/O pad and the second voltage terminal, or a sixth diode coupled to the third diode in parallel.

5 . The semiconductor device of claim 1 , further comprising:
a fourth diode, wherein a first terminal and a second terminal of the fourth diode are coupled to the second voltage terminal, wherein the fourth diode and the third diode include a second semiconductor structure configured to direct a third part of the ESD current, from the second voltage terminal to the first voltage terminal, or from the first voltage terminal to the second voltage terminal.

6 . The semiconductor device of claim 5 , wherein
the third diode and the fourth diode are configured to operate as an equivalent silicon controlled rectifier (SCR) circuit.

7 . The semiconductor device of claim 5 ,
wherein the first semiconductor structure comprises:
a substrate;
a first well of a first type disposed on the substrate;
a first doped region of the first type disposed in the first well and configured as the second terminal of the second diode;
a second doped region of a second type disposed in the first well and configured as the first terminal of the second diode;
a second well of the second type disposed on the substrate and adjacent to the first well;
a third doped region of the first type disposed in the second well and configured as the first terminal of the third diode; and
a fourth doped region of the second type disposed in the second well and configured as the second terminal of the third diode;
wherein the second doped region, the first well, the substrate, the second well, and the third doped region are configured to operate as an equivalent silicon controlled rectifier (SCR) circuit;
wherein the second semiconductor structure comprises:
the substrate;
the third doped region;
the fourth doped region;
a third well of a first type disposed on the substrate and adjacent to the second well;
a fifth doped region of the first type disposed in the third well and configured as the first terminal of the fourth diode; and
a sixth doped region of the second type disposed in the third well and configured as the second terminal of the fourth diode;
wherein the third doped region, the second well, the substrate, the third well, and the sixth doped region are configured to operate as a second equivalent silicon controlled rectifier circuit.

8 . A method, comprising:
conducting a first electrostatic discharge (ESD) path between an input/output (I/O) pad and a first voltage terminal that is configured to receive a first supply voltage, wherein in the first ESD path, a first diode is coupled between the I/O pad and a second voltage terminal that is configured to receive a second supply voltage, and a clamp circuit is coupled between the first voltage terminal and the second voltage terminal; and conducting a second ESD path between the I/O pad and the first voltage terminal, wherein in the second ESD path, the first diode and a second diode having two terminals that are coupled to the first voltage terminal include a first semiconductor structure, and the first semiconductor structure is configured to operate as a first equivalent silicon controlled rectifier (SCR) circuit.

9 . The method of claim 8 , further comprising:
conducting a third ESD path between the first voltage terminal and the second voltage terminal, wherein in the third ESD path, the second diode and a third diode having two terminals that are coupled to the second voltage terminal include a second semiconductor structure, and the second semiconductor structure is configured to operate as a second equivalent SCR circuit.

10 . The method of claim 8 , wherein a third diode is disposed at a side of the first diode, wherein the third diode comprises a well of a first type, a first doped region of a second type coupled to the I/O pad, and at least one second doped region of the first type coupled to the first voltage terminal.

11 . The method of claim 10 , wherein the at least one second doped region comprises a plurality of second doped regions each having a strap configuration in a plain view, wherein the plurality of second doped regions are arranged along a first direction.

12 . The method of claim 8 , further comprising:
conducting a third ESD path between the I/O pad and the first voltage terminal, wherein in the third ESD path, the first diode and a third diode having two terminals that are coupled to the first voltage terminal include a second semiconductor structure, and the second semiconductor structure is configured to operate as a second equivalent silicon controlled rectifier circuit, wherein a voltage level of the first voltage terminal is lower than that of the second voltage terminal.

13 . A semiconductor device, comprising:
a first diode having a plurality of first doped straps that extend in a first direction and configured as a plurality of terminals coupled to a first voltage terminal; and a second diode having a second doped strap that extends in the first direction and is separated from the plurality of first doped

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Peng Po-Lin
• Chu Li-Wei
• Tsai Ming-Fu
• Lee Jam-Wem
• Su Yu-Ti

Classifications

• H10W42/80

  protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10W42/60

  protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) · CPC title

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D84/615

  Combinations of vertical BJTs and one or more of resistors or capacitors · CPC title