Majority gate based low power ferroelectric based adder with reset mechanism

Patent metadata

Field	Value
Publication number	US-2022190831-A1
Application number	US-202217654055-A
Country	US
Kind code	A1
Filing date	Mar 8, 2022
Priority date	Dec 27, 2019
Publication date	Jun 16, 2022
Grant date	—

Abstract

An adder with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals are driven to first terminals of non-ferroelectric capacitors while the second terminals are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate. A reset mechanism initializes the non-linear polar capacitor before addition function is performed.

First claim

We claim:

1 . An apparatus comprising:
a plurality of majority gates coupled together as a 1-bit full-adder, wherein an individual majority gate includes non-linear polar material, wherein an individual majority gate includes a plurality of inputs; a plurality of driver circuitries coupled to the plurality of inputs; and a reset mechanism comprising a first set of devices coupled to outputs of the plurality of driver circuitries, and a second set of devices coupled to the non-linear polar material.

2 . The apparatus of claim 1 , wherein the first set of devices include:
a plurality of pass-gates coupled to the outputs of the plurality of driver circuitries, wherein an individual pass-gate in controllable by a first control input and a second control input, wherein the second control input is an inverse of the first control input.

3 . The apparatus of claim 2 , wherein the first set of devices further include:
a plurality of pull-down devices coupled to the plurality of pass-gates and the plurality of inputs, wherein an individual pull-down device is coupled to the individual pass-gate, and wherein the individual pull-down device is controllable by the first control input.

4 . The apparatus of claim 3 , wherein the second set of devices include:
pull-down devices coupled to either terminal of a capacitor having the non-linear polar material, wherein the pull-down devices include a first transistor controllable by the first control input, and a second transistor controllable by a third control input.

5 . The apparatus of claim 4 , wherein the second set of devices include:
a pull-up device coupled to a first terminal of the capacitor, wherein the first terminal is coupled to an output of the plurality of majority gates, wherein the pull-up device is controllable by fourth control input.

6 . The apparatus of claim 5 , wherein the reset mechanism is to operate in four phases in a sequence.

7 . The apparatus of claim 6 , wherein the four phases include a first phase to initialize input capacitors of the plurality of majority gates by control of the first control input and the second control input.

8 . The apparatus of claim 7 , wherein the four phases include a second phase to initialize the capacitor having the non-linear polar material by control of the fourth control input.

9 . The apparatus of claim 8 , wherein the four phases include a third phase to initialize the capacitor having the non-linear polar material by control of the first control input, the third control input, and the fourth control input.

10 . The apparatus of claim 9 , wherein the four phases include a fourth phase to open the plurality of pass-gates by control of the first control input and the second control input, and to disable other devices of the first set of devices and the second set of devices.

11 . The apparatus of claim 1 , wherein the reset mechanism is operable to initialize nodes of the individual majority gate to 0V.

12 . The apparatus of claim 1 , wherein the plurality of inputs includes a first input, a second input, and a carry-in input, wherein the plurality of majority gates include:
a first 3-input majority gate to receive the first input, the second input, and the carry-in input; a first inversion logic having an input coupled to the carry-in input, and an output; a second 3-input majority gate to receive the first input, the second input, and the output of the first inversion logic; a second inversion logic having an input coupled to an output of the first 3-input majority gate, and an output; a non-inversion logic coupled to an output of the second 3-input majority gate; and a third 3-input majority gate to receive the output of the second inversion logic, the output of the non-inversion logic, and the carry-in input, wherein an individual one of the first, second, and third 3-input majority gates include a capacitor having the non-linear polar material.

13 . The apparatus of claim 12 , wherein the plurality of majority gates include:
a third inversion logic having an input coupled to the output of the second inversion logic, and an output which is a carry-out.

14 . The apparatus of claim 13 , wherein the non-inversion logic is a first non-inversion logic, wherein the apparatus comprising a second non-inversion logic coupled to an output of the third 3-input majority gate.

15 . The apparatus of claim 1 , wherein the non-linear polar material includes one of:
ferroelectric material, para-electric material, or non-linear dielectric.

16 . The apparatus of claim 15 , wherein the ferroelectric material includes one of:
Bismuth ferrite (BFO), BFO with a doping material where in the doping material is one of Lanthanum, or elements from lanthanide series of periodic table; Lead zirconium titanate (PZT), or PZT with a doping material, wherein the doping material is one of La or Nb; relaxor ferro-electric which includes one of lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lead lanthanum zirconate titanate (PLZT), lead scandium niobate (PSN), Barium Titanium-Bismuth Zinc Niobium Tantalum (BT-BZNT), or Barium Titanium-Barium Strontium Titanium (BT-BST); perovskite ferroelectrics includes one of: BaTiO3, PbTiO3, KNbO3, or NaTaO3; hexagonal ferroelectric includes one of: YMnO3 or LuFeO3; hexagonal ferroelectrics of a type h-RMnO3, where R is a rare earth element including one of: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), holmium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), praseodymium (Pr), promethium (Pm), samarium (Sm), scandium (Sc), terbium (Tb), thulium (Tm), ytterbium (Yb), or yttrium (Y); Hafnium (Hf), Zirconium (Zr), Aluminum (Al), Silicon (Si), their oxides or their alloyed oxides; Hafnium oxides as Hf1-x Ex Oy where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-x-y)Mg(x)Nb(y)N, y doped HfO2, where x includes one of: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein ‘x’ is a fraction; Niobate type compounds LiNbO3, LiTaO3, Lithium iron Tantalum Oxy Fluoride, Barium Strontium Niobate, Sodium Barium Niobate, or Potassium strontium niobate; or improper ferroelectric includes one of: [PTO/STO]n or [LAO/STO]n, where ‘n’ is between 1 to 100.

17 . An apparatus comprising:
a plurality of majority gates coupled together as a 1-bit full-adder, wherein an individual majority gate includes a capacitor having non-linear polar material, wherein an individual majority gate includes a plurality of inputs; a plurality of driver circuitries coupled to the plurality of inputs; and a reset mechanism to operate in four separate phases to initialize the plurality of inputs and voltages across the capacitor.

18 . The apparatus of claim 17 , wherein the plurality of inputs are an analog signal, a digital signal, or a combination of them.

19 . A system comprising:
a processor circuitry; a communication interface communicatively coupled to the processor circuitry; and a memory coupled to the processor circuitry, wherein the processor circuitry comprises a 1-bit full-adder which includes a plurality of majority gates, wherein an individual majority gate includes non-linear polar material, wherein an individual majority gate includes a plurality of inputs, wherein the processor circuitry includes a reset mechanism comprising a first set of devices coupled to outputs of a plurality of driver circuitries, and a second set of devices coupled to the non-

Assignees

• Kepler Computing Inc

Inventors

• Manipatruni Sasikanth
• Fang Yuan-Sheng
• Menezes Robert
• Dokania Rajeev Kumar
• Thareja Guarav
• Ramesh Ramamoorthy
• Mathuriya Amrita

Classifications

• H10D1/694

  comprising noble metals or noble metal oxides · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H03K19/23 Primary

  Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs · CPC title

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• H01L28/65

  Electricity · mapped topic