Semiconductor device with reduced contact resistance

Patent metadata

Field	Value
Publication number	US-2022181446-A1
Application number	US-202117370551-A
Country	US
Kind code	A1
Filing date	Jul 8, 2021
Priority date	Dec 7, 2020
Publication date	Jun 9, 2022
Grant date	—

Abstract

A semiconductor device includes an active region on a substrate, a gate structure on the substrate and intersecting the active region, a source/drain region on the active region on both sides of the gate structure and including silicon (Si), and a contact structure on the source/drain region. The source/drain region includes a shallow doping region doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region. A concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to an upper surface of the substrate.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an active region on a substrate; a gate structure on the substrate, wherein the gate structure intersects the active region; a source/drain region on the active region and on a side of the gate structure and comprising silicon (Si); and a contact structure on the source/drain region, wherein the source/drain region comprises a shallow doping region that is doped with germanium (Ge) and is in an upper region including an upper surface of the source/drain region, and wherein a concentration of germanium (Ge) in the shallow doping region gradually decreases from the upper surface of the source/drain region toward an upper surface of the substrate in a direction that is perpendicular to the upper surface of the substrate.

2 . The semiconductor device of claim 1 , wherein a depth of the shallow doping region in the direction perpendicular to the upper surface of the substrate is in a range of about 2 nm to about 6 nm.

3 . The semiconductor device of claim 1 ,
wherein the source/drain region further comprise a first epitaxial region and a second epitaxial region sequentially stacked on the active region, wherein the source/drain region has a P-type conductivity, wherein each of the first epitaxial region and the second epitaxial region comprises silicon (Si) and germanium (Ge), and wherein a concentration of germanium (Ge) in the second epitaxial region is higher than a concentration of germanium (Ge) in the first epitaxial region and is lower than the concentration of germanium (Ge) in the shallow doping region.

4 . The semiconductor device of claim 3 , wherein, in the shallow doping region, an atomic percentage of germanium (Ge) with respect to silicon (Si) is in a range of about 50 at % to about 100 at %.

5 . The semiconductor device of claim 4 , wherein, in the shallow doping region, the atomic percentage of germanium (Ge) with respect to silicon (Si) gradually decreases from about 100 at % adjacent the upper surface of the source/drain region to about 50 at %, in the direction towards the upper surface of the substrate.

6 . The semiconductor device of claim 1 ,
wherein the source/drain region further comprises a third epitaxial region, wherein the source/drain region has an N-type conductivity, and wherein the third epitaxial region comprises silicon (Si).

7 . The semiconductor device of claim 6 , wherein an atomic percentage of germanium (Ge) doped in the shallow doping region with respect to silicon (Si) included in the shallow doping region gradually decreases from about 100 at % adjacent the upper surface of the source/drain region to less than about 1 at %, in the direction towards the upper surface of the substrate.

8 . The semiconductor device of claim 1 ,
wherein the contact structure comprises a metal-semiconductor compound layer on the shallow doping region and a contact plug on the metal-semiconductor compound layer, and wherein an upper end of the shallow doping region is recessed toward the upper surface of the substrate.

9 . The semiconductor device of claim 1 , wherein a lower end of the contact structure is on substantially a same level as the upper surface of the source/drain region.

10 . The semiconductor device of claim 1 , wherein a lower end of the contact structure is closer than an uppermost surface of the source/drain region to the substrate.

11 . The semiconductor device of claim 10 , wherein a distance from a lateral surface of the contact structure to a side end of the shallow doping region is substantially equal to or less than a distance from the lower end of the contact structure to a lower end of the shallow doping region.

12 . The semiconductor device of claim 10 , wherein a depth of the shallow doping region from the uppermost surface of the source/drain region is in a range of about 2 nm to about 6 nm.

13 . The semiconductor device of claim 12 , wherein a distance from a lateral surface of the contact structure to a side end of the shallow doping region is greater than a distance from the lower end of the contact structure to a lower end of the shallow doping region.

14 . The semiconductor device of claim 1 , further comprising:
a channel layer that extends perpendicular to the upper surface of the substrate on the active region, wherein the gate structure overlaps an upper surface and a lateral surface of the channel layer.

15 . The semiconductor device of claim 1 , further comprising:
a plurality of channel layers spaced apart from each other perpendicular to the upper surface of the substrate on the active region, wherein the gate structure surrounds the plurality of channel layers in a plan view of the semiconductor device.

16 . A semiconductor device comprising:
an active region on a substrate, wherein the active region extends in a first direction; a gate structure on the substrate, intersecting the active region, and extending in a second direction; and a source/drain region on the active region and on a side of the gate structure and comprising silicon (Si), wherein the source/drain region comprises a shallow doping region doped with germanium (Ge) and in an upper region that includes an upper surface of the source/drain region, and an epitaxial region below the shallow doping region, wherein a thickness of the epitaxial region in a third direction that is perpendicular to an upper surface of the substrate is greater than a thickness of the shallow doping region in the third direction, and wherein an atomic percentage of germanium (Ge) with respect to silicon (Si) adjacent the upper surface of the source/drain region is in a range of about 95 at % to about 100 at %.

17 . The semiconductor device of claim 16 , wherein a concentration of germanium (Ge) doped in the shallow doping region gradually decreases from the upper surface of the source/drain region toward the upper surface of the substrate in the third direction.

18 . The semiconductor device of claim 16 , wherein a depth of the shallow doping region is in a range of about 2 nm to about 6 nm.

19 . A semiconductor device comprising:
an active region on a substrate; a gate structure on the substrate, wherein the gate structure intersects the active region; and a source/drain region on the active region on at least one side of the gate structure, wherein the source/drain region comprises a first region having a depth of about 2 nm to about 6 nm from an upper surface of the source/drain region, and wherein, in the first region, a concentration of germanium (Ge) in the source/drain region gradually decreases as a depth of the source/drain region from the upper surface of the source/drain region increases.

20 . The semiconductor device of claim 19 , wherein the source/drain region further comprises:
a second region below the first region and including silicon (Si) and germanium (Ge); and a third region below the second region and including silicon (Si) and germanium (Ge), wherein, in the third region, a concentration of germanium (Ge) gradually decreases as a depth of the source/drain region from the upper surface of the source/drain region increases.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hong Sahwan
• Lee Hanki
• Lee Jeongmin

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title