Integrated piezoelectric microelectromechanical ultrasound transducer (pmut) on integrated circuit (ic) for fingerprint sensing

US2022172506A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2022172506-A1
Application numberUS-202217675832-A
CountryUS
Kind codeA1
Filing dateFeb 18, 2022
Priority dateNov 28, 2012
Publication dateJun 2, 2022
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Microelectromechanical (MEMS) devices and associated methods are disclosed. Piezoelectric MEMS transducers (PMUTs) suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuit (IC), as well as PMUT arrays having high fill factor for fingerprint sensing, are described.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method, comprising: forming a plurality of cavities in a complementary metal oxide semiconductor (CMOS) device wafer; depositing and patterning a piezoelectric layer over the plurality of cavities; forming a plurality of openings in the piezoelectric layer to expose a first conductive material layer under the piezoelectric layer and to expose at least one CMOS device wafer electrode; and depositing and patterning a second conductive material layer over the piezoelectric layer to establish an electrical connection between the at least one CMOS device wafer electrode and the second conductive material layer. 2 . The method of claim 1 , wherein the forming the plurality of cavities comprises forming a piezoelectric MUT (PMUT) array of a fingerprint sensor adapted to sense a characteristic of a fingerprint placed adjacent to the PMUT array and opposite the plurality of cavities. 3 . The method of claim 1 , wherein the forming a plurality of cavities further comprises: filling the plurality of cavities in the CMOS device wafer with sacrificial material; planarizing the sacrificial material on the CMOS device wafer; depositing a capping layer over the sacrificial material; forming at least one opening in the capping layer to expose the sacrificial material; selectively removing the sacrificial material; and sealing the at least one opening in the capping layer. 4 . The method of claim 3 , further comprising: depositing the first conductive material layer comprising a metal conductive layer over the capping layer. 5 . The method of claim 1 , wherein the depositing and patterning the piezoelectric layer comprises depositing and patterning at least one of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3). 6 . The method of claim 1 , wherein the forming the plurality of openings in the piezoelectric layer and the depositing and patterning the second conductive material layer over the piezoelectric layer comprises forming at least one bottom electrode electrically coupled to at least one top electrode via the piezoelectric layer. 7 . The method of claim 6 , further comprising: depositing an acoustic propagation layer over the at least one top electrode. 8 . The method of claim 7 , further comprising: depositing a cover layer over the acoustic propagation layer. 9 . The method of claim 7 , wherein the depositing the acoustic propagation layer comprises depositing at least one of a liquid, a polymer, or an acoustic impedance matching material configured to provide acoustic impedance matching between a PMUT device associated with the at least one top electrode and the cover layer. 10 . A microelectromechanical systems (MEMS) device; a complementary metal oxide semiconductor (CMOS) device wafer associated with a piezoelectric MEMS ultrasound transducer (PMUT) array of a fingerprint sensor and having a plurality of cavities configured in an array; a first metal conductive layer disposed on the CMOS device wafer and over the plurality of cavities; a piezoelectric material disposed on the first metal conductive layer; and a second metal conductive layer, disposed on the piezoelectric material, electrically coupling the second metal conductive layer and at least one CMOS device wafer electrode, and electrically coupling the first metal conductive layer to at least one other CMOS device wafer electrode, wherein the plurality of cavities, the piezoelectric material, the first metal conductive layer, and the second metal conductive layer are configured as a plurality of PMUT structures. 11 . The MEMS device of claim 10 , wherein the plurality of PMUT structures are formed integrally to a CMOS structure, and wherein the fingerprint sensor is adapted to sense a characteristic of a fingerprint placed adjacent to the PMUT array and opposite the plurality of cavities. 12 . The MEMS device of claim 10 , wherein the piezoelectric material comprises at least one of aluminum nitride, lead zirconate titanate (PZT), zinc oxide, polyvinylidene difluoride (PVDF), lithium niobate (LiNbO3). 13 . The MEMS device of claim 10 , further comprising: at least one bottom electrode electrically coupled to at least one top electrode via the piezoelectric material. 14 . The MEMS device of claim 13 , further comprising: an acoustic propagation layer disposed over the at least one top electrode.

Assignees

Inventors

Classifications

  • Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function · CPC title

  • Forming interconnections between the electronic processing unit and the micromechanical structure · CPC title

  • non-optical, e.g. ultrasonic or capacitive sensing · CPC title

  • Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias · CPC title

  • Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

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What does patent US2022172506A1 cover?
Microelectromechanical (MEMS) devices and associated methods are disclosed. Piezoelectric MEMS transducers (PMUTs) suitable for integration with complementary metal oxide semiconductor (CMOS) integrated circuit (IC), as well as PMUT arrays having high fill factor for fingerprint sensing, are described.
Who is the assignee on this patent?
Invensense Inc
What technology area does this patent fall under?
Primary CPC classification G06V40/1306. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jun 02 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).