Driving circuit of display panel, method of driving display panel, and display panel

Patent metadata

Field	Value
Publication number	US-2022157219-A1
Application number	US-202017424519-A
Country	US
Kind code	A1
Filing date	Sep 30, 2020
Priority date	Sep 30, 2020
Publication date	May 19, 2022
Grant date	—

Abstract

A method of driving a display panel, a driving circuit of a display panel, and a display panel are disclosed. The display panel includes a multiplexing unit and a plurality of pixels arranged in an array of M rows and N columns, the multiplexing unit includes a plurality of thin film transistors, and each thin film transistor includes a gate electrode applied with a multiplexing unit gate signal. The method includes: acquiring a plurality of data signals for driving i-th row of pixels, where 1≤i≤M; generating multiplexing unit gate signals for respective thin film transistors of the multiplexing unit based on the plurality of data signals; and applying the multiplexing unit gate signals to gate electrodes of the respective thin film transistors, so that the respective thin film transistors are turned on or turned off. The multiplexing unit gate signals change according to changes of the plurality of data signals.

First claim

1 . A method of driving a display panel, wherein the display panel comprises a multiplexing unit and a plurality of pixels arranged in an array of M rows and N columns, the multiplexing unit comprises a plurality of thin film transistors, and each thin film transistor of the multiplexing unit comprises a gate electrode applied with a multiplexing unit gate signal, a first electrode applied with a data signal, and a second electrode electrically connected to a pixel driving circuit of a pixel; and wherein the method comprises:
acquiring a plurality of data signals for driving i-th row of pixels, where 1≤i≤M; generating multiplexing unit gate signals for respective thin film transistors of the multiplexing unit based on the plurality of data signals; and applying the multiplexing unit gate signals to gate electrodes of the respective thin film transistors, so that the respective thin film transistors of the multiplexing unit are turned on or turned off, wherein the multiplexing unit gate signals change according to changes of the plurality of data signals.

2 . The method of claim 1 , wherein the plurality of data signals for driving the i-th row of pixels comprise a plurality of positive voltage signals and a plurality of negative voltage signals, and the method further comprises:
determining a maximum positive voltage which has a maximum value among the plurality of positive voltage signals; and determining a minimum negative voltage which has a minimum absolute value among the plurality of negative voltage signals.

3 . The method of claim 2 , wherein the generating the multiplexing unit gate signals for the respective thin film transistors of the multiplexing unit based on the plurality of data signals comprises:
determining a sum of the maximum positive voltage and a threshold voltage of the thin film transistor as a first turn-on voltage threshold, in response to that the data signals are positive voltage signals; and generating the multiplexing unit gate signals which are greater than the first turn-on voltage threshold.

4 . The method of claim 2 , wherein the generating the multiplexing unit gate signals for the respective thin film transistors of the multiplexing unit based on the plurality of data signals comprises:
in response to that the data signals are negative voltage signals, comparing a sum of the minimum negative voltage and a threshold voltage of the thin film transistor with zero and determining a greater one of the sum and zero as a second turn-on voltage threshold; and generating the multiplexing unit gate signals which are greater than the second turn-on voltage threshold.

5 . The method of claim 2 , wherein the generating the multiplexing unit gate signals for the respective thin film transistors of the multiplexing unit based on the plurality of data signals comprises:
determining zero as a first turn-off voltage threshold in response to that the data signals are positive voltage signals; and generating the multiplexing unit gate signals which are smaller than the first turn-off voltage threshold.

6 . The method of claim 2 , wherein the generating the multiplexing unit gate signals for the respective thin film transistors of the multiplexing unit based on the plurality of data signals comprises:
in response to that the data signals are negative voltage signal, comparing a sum of the minimum negative voltage and a threshold voltage of the thin film transistor with zero and determining a smaller one of the sum and zero as a second turn-off voltage threshold; and generating the multiplexing unit gate signals which are smaller than the second turn-off voltage threshold.

7 . The method of claim 1 , wherein each pixel comprises a first primary-color sub-pixel, a second primary-color sub-pixel, and a third primary-color sub-pixel, and in the same frame, voltages of a plurality of data signals for driving a plurality of columns of sub-pixels with the same primary color have the same polarity.

8 . A driving circuit of a display panel, wherein the display panel comprises a multiplexing unit and a plurality of pixels arranged in an array of M rows and N columns, the multiplexing unit comprises a plurality of thin film transistors, and each thin film transistor of the multiplexing unit comprises a gate electrode applied with a multiplexing unit gate signal, a first electrode applied with a data signal, and a second electrode electrically connected to a pixel driving circuit of a pixel; and wherein the driving circuit comprises:
an acquisition circuit configured to acquire a plurality of data signals for driving i-th row of pixels, where 1≤i≤M; and a generation circuit configured to generate multiplexing unit gate signals for respective thin film transistors of the multiplexing unit based on the plurality of data signals, wherein the generation circuit is electrically connected to gate electrodes of the respective thin film transistors so as to apply the multiplexing unit gate signals to the gate electrodes of the respective thin film transistors, so that the respective thin film transistors of the multiplexing unit are turned on or turned off; and wherein the multiplexing unit gate signals change according to changes of the plurality of data signals.

9 . The driving circuit of claim 8 , further comprising a comparison circuit, wherein the comparison circuit is configured to:
determine a maximum positive voltage which has a maximum value among a plurality of positive voltage signals; and determine a minimum negative voltage which has a minimum absolute value among a plurality of negative voltage signals.

10 . The driving circuit of claim 9 , wherein the generation circuit is further configured to:
determine a sum of the maximum positive voltage and a threshold voltage of the thin film transistor as a first turn-on voltage threshold, in response to that the data signals are positive voltage signals; and generate the multiplexing unit gate signals which are greater than the first turn-on voltage threshold.

11 . The driving circuit of claim 9 , wherein the generation circuit is further configured to:
in response to that the data signals are negative voltage signals, compare a sum of the minimum negative voltage and a threshold voltage of the thin film transistor with zero and determine a greater one of the sum and zero as a second turn-on voltage threshold; and generate the multiplexing unit gate signals which are greater than the second turn-on voltage threshold.

12 . The driving circuit of claim 9 , wherein the generation circuit is further configured to:
determine zero as a first turn-off voltage threshold in response to that the data signals are positive voltage signals; and generate the multiplexing unit gate signals which are smaller than the first turn-off voltage threshold.

13 . The driving circuit of claim 9 , wherein the generation circuit is further configured to:
in response to that the data signals are negative voltage signal, compare a sum of the minimum negative voltage and a threshold voltage of the thin film transistor with zero and determine a smaller one of the sum and zero as a second turn-off voltage threshold; and generate the multiplexing unit gate signals which are smaller than the second turn-off voltage threshold.

14 . A display panel comprising the driving circuit of claim 8 .

Assignees

• Beijing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zhao Jing
• Chen Xiuyun
• Zhang Yehao
• Liang Dapeng
• Shi Meng
• Huang Yadong
• Xu Zhenguo

Classifications

• G09G2310/0275

  Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G3/2003 Primary

  Display of colours (specific for liquid crystal displays G09G3/3607) · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title