Circuit and method for spike time dependent plasticity

Patent metadata

Field	Value
Publication number	US-2022147796-A1
Application number	US-202117454373-A
Country	US
Kind code	A1
Filing date	Nov 10, 2021
Priority date	Nov 12, 2020
Publication date	May 12, 2022
Grant date	—

Abstract

The present disclosure relates to a neuron circuit of a spiking neural network comprising: a first resistive switching memory device having a conductance that decays over time; and a programming circuit configured to reset the resistive state of the first resistive switching element in response to a spike in an output voltage of the neuron circuit.

First claim

1 . A spiking neural network comprising:
a pre-synaptic neuron circuit comprising a first resistive switching memory device having a conductance that decays over time; a post-synaptic neuron circuit comprising a second resistive switching memory device having a conductance that decays over time; and one or more programming circuits configured to reset the resistive state of the first resistive switching element in response to a spike in an output voltage of the pre-synaptic neuron circuit and to reset the resistive state of the second resistive switching element in response to a spike in an output voltage of the post-synaptic neuron circuit; and a synapse circuit coupling the pre-synaptic neuron circuit to the post-synaptic neuron circuit, wherein the synapse circuit comprises a further resistive memory device configured to store a synaptic weight, wherein the one or more programming circuits, or a further programming circuit, is configured to update the synaptic weight in response to a spike in the output voltage of the post-synaptic neuron circuit based on a conductance value of the first resistive switching memory device and to update the synaptic weight in response to a spike in the output voltage of the pre-synaptic neuron circuit based on a conductance value of the second resistive switching memory device.

2 . The spiking neural network of claim 1 , wherein the first resistive switching memory device is a phase change memory device or a conductive-bridging random-access memory device.

3 . The spiking neural network of claim 1 , further comprising a control circuit configured, in response to a spike in the output voltage of the post-synaptic neuron circuit, to read the conductance value of the first resistive switching memory device, to compare the conductance value with a first threshold, and to update the synaptic weight by increasing the conductance of the further resistive memory device if the conductance value exceeds the first threshold.

4 . The spiking neural network of claim 3 , wherein, in the case that the conductance value does not exceed the first threshold, the control circuit is further configured to compare the conductance value with a second threshold, and to update the synaptic weight by decreasing the conductance of the further resistive memory device if the conductance value exceeds the second threshold.

5 . The spiking neural network of claim 3 , wherein the control circuit is further configured, in response to a spike in the output voltage of the pre-synaptic neuron circuit, to read the conductance value of the second resistive switching memory device, to compare the conductance value of the second resistive switching memory device with a third threshold, and to update the synaptic weight by decreasing the conductance of the further resistive memory device if the conductance value exceeds the third threshold.

6 . A learning method for a spiking neural network, the method comprising:
resetting, by one or more programming circuits: the resistive state of a first resistive switching element of a pre-synaptic neuron circuit in response to a spike in an output voltage of the pre-synaptic neuron circuit; and the resistive state of a second resistive switching element of a post-synaptic neuron circuit in response to a spike in an output voltage of the post-synaptic neuron circuit; and storing, by the one or more programming circuits or by another programming circuit, a synaptic weight to a further resistive memory device of a synapse circuit coupling the pre-synaptic neuron circuit to the post synaptic neuron circuit; and updating the synaptic weight in response to a spike in the output voltage of the post-synaptic neuron circuit based on a conductance value of the first resistive switching memory device and updating the synaptic weight in response to a spike in the output voltage of the pre-synaptic neuron circuit based on a conductance value of the second resistive switching memory device.

7 . The method of claim 6 , further comprising, in response to a spike in the output voltage of the post-synaptic neuron circuit:
reading, by a control circuit, the conductance value of the first resistive switching memory device; comparing the conductance value with a first threshold; and updating the synaptic weight by increasing the conductance of the further resistive memory device if the conductance value exceeds the first threshold.

8 . The method of claim 7 , further comprising, in the case that the conductance value does not exceed the first threshold:
comparing the conductance value with a second threshold; and updating the synaptic weight by decreasing the conductance of the further resistive memory device if the conductance value exceeds the second threshold.

9 . The method of claim 7 , further comprising, in response to a spike in the output voltage of the pre-synaptic neuron circuit:
reading, by the control circuit, the conductance value of the second resistive switching memory device; comparing the conductance value of the second resistive switching memory device with a third threshold; and updating the synaptic weight by decreasing the conductance of the further resistive memory device if the conductance value exceeds the third threshold.

Assignees

• Commissaria A Ienergie Atomique Et Aux Energies Alternatives
• Univ Zuerich

Inventors

• Dalgaty Thomas
• Vianello Elisa
• Moro Filippo
• Indiveri Giacomo
• Payvand Melika

Classifications

• G06N3/049 Primary

  Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title

• G06N3/065

  Analogue means · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G06N3/088

  Non-supervised learning, e.g. competitive learning · CPC title

• G06N3/0635

  Physics · mapped topic