Bus slave circuit and related single-wire bus apparatus

Patent metadata

Field	Value
Publication number	US-2022147474-A1
Application number	US-202017095204-A
Country	US
Kind code	A1
Filing date	Nov 11, 2020
Priority date	Nov 11, 2020
Publication date	May 12, 2022
Grant date	—

Abstract

A single-wire bus apparatus that includes a bus slave circuit(s) is provided. The bus slave circuit(s) can receive a unicast, a multicast, and/or a broadcast command sequence over a single-wire bus. In embodiments disclosed herein, the bus slave circuit(s) can be configured to determine whether to respond to a received multicast or broadcast command sequence based on a predefined response policy. As such, the single-wire bus apparatus can be configured to mix and match a legacy slave circuit(s), which always responds to the received multicast or broadcast command sequence, with an enhanced slave circuit(s) that can decide whether to respond to the received multicast or broadcast command sequence based on the predefined response policy. As a result, it is possible to improve design and implementation flexibility, such as supporting more bus slave circuits per port.

First claim

1 . A bus slave circuit comprising:
a slave port coupled to a single-wire bus; and a controller configured to:
receive a command sequence via the slave port;
determine whether the received command sequence is one of a multicast command sequence comprising a group slave identification (GSID) and a broadcast command sequence comprising a broadcast slave identification (BSID); and
in response to determining that the received command sequence is one of the multicast command sequence and the broadcast command sequence:
determine whether to respond to the received command sequence based on a predefined response policy; and
assert an acknowledgement signal on the single-wire bus in response to determining to respond to the received command sequence.

2 . The bus slave circuit of claim 1 wherein the controller is further configured not to assert the acknowledgement signal on the single-wire bus in response to determining not to respond to the received command sequence.

3 . (canceled)

4 . The bus slave circuit of claim 1 further comprising a slave register configured to store the predefined response policy, wherein the predefined response policy comprises:
a position indicator configured to indicate a preassigned position number of the bus slave circuit; and
a response indicator configured to indicate whether the bus slave circuit will respond to the received command sequence.

5 . The bus slave circuit of claim 4 wherein the controller is provided in a legacy bus slave circuit and further configured to determine to respond to the received command sequence when the preassigned position number is smaller than or equal to a threshold number, independent of the response indicator.

6 . The bus slave circuit of claim 4 wherein the controller is provided in an enhanced bus slave circuit and further configured to:
determine to respond to the received command sequence when the preassigned position number is smaller than or equal to a threshold number and the response indicator is set to TRUE; and
determine not to respond to the received command sequence under one of following conditions:
the preassigned position number is smaller than or equal to the threshold number and the response indicator is set to FALSE; and
the preassigned position number is greater than the threshold number.

7 . The bus slave circuit of claim 1 wherein the controller is further configured to:
determine that the command sequence is a unicast command sequence associated with a unique slave identification (USID); and
assert the acknowledgement signal on the single-wire bus in response to receiving the unicast command sequence and independent of the predefined response policy.

8 . A single-wire bus apparatus comprising:
a single-wire bus consisting of one wire; and a plurality of bus slave circuits each comprising:
a slave port coupled to the single-wire bus; and
a controller configured to:
receive a command sequence via the slave port;
determine whether the received command sequence is one of a multicast command sequence comprising a group slave identification (GSID) and a broadcast command sequence comprising a broadcast slave identification (BSID); and
in response to determining that the received command sequence is one of the multicast command sequence and the broadcast command sequence:
determine whether to respond to the received command sequence based on a predefined response policy; and
assert an acknowledgement signal in response to determining to respond to the received command sequence.

9 . The single-wire bus apparatus of claim 8 further comprising a bridge circuit coupled to the plurality of bus slave circuits via the single-wire bus and configured to communicate the command sequence to any one or more of the plurality of bus slave circuits via the single-wire bus.

10 . The single-wire bus apparatus of claim 9 wherein the bridge circuit is further coupled to a radio frequency front-end (RFFE) master circuit via an RFFE bus, the bridge circuit is configured to bridge communications between the RFFE master circuit and any one or more of the plurality of bus slave circuits.

11 . The single-wire bus apparatus of claim 9 wherein the bridge circuit comprises:
at least one first bus port coupled to a first subset of five or more of the plurality of bus slave circuits; and
at least one second bus port coupled to a second subset of five or more of the plurality of bus slave circuits different from the first subset of five or more of the plurality of bus slave circuits.

12 . The single-wire bus apparatus of claim 9 wherein the bridge circuit is configured to communicate the command sequence as one of:
the multicast command sequence associated with the GSID identifying any two or more of the plurality of bus slave circuits; and
the broadcast command sequence associated with the BSID identifying the plurality of bus slave circuits.

13 . The single-wire bus apparatus of claim 12 wherein the controller is further configured not to assert the acknowledgement signal on the single-wire bus in response to determining not to respond to the received command sequence.

14 . The single-wire bus apparatus of claim 13 wherein the bridge circuit is further configured to assert the acknowledgement signal on the single-wire bus on behalf of any of the plurality of bus slave circuits that determines not to respond to the received command sequence.

15 . The single-wire bus apparatus of claim 12 wherein each of the plurality of bus slave circuits further comprises a slave register configured to store the predefined response policy, wherein the predefined response policy comprises:
a position indicator configured to indicate a preassigned position number of any of the plurality of bus slave circuits; and
a response indicator configured to indicate whether the any of the plurality of bus slave circuits will respond to the received command sequence.

16 . The single-wire bus apparatus of claim 15 wherein the controller is provided in a legacy bus slave circuit and further configured to determine to respond to the received command sequence when the preassigned position number is smaller than or equal to a threshold number, independent of the response indicator.

17 . The single-wire bus apparatus of claim 15 wherein the controller is provided in an enhanced bus slave circuit and further configured to:
determine to respond to the received command sequence when the preassigned position number is smaller than or equal to a threshold number and the response indicator is set to TRUE; and
determine not to respond to the received command sequence under one of following conditions:
the preassigned position number is smaller than or equal to the threshold number and the response indicator is set to FALSE; and
the preassigned position number is greater than the threshold number.

18 . The single-wire bus apparatus of claim 15 wherein the bridge circuit comprises a master register circuit configured to store the predefined response policy associated with each of the plurality of bus slave circuits.

19 . The single-wire bus apparatus of claim 9 wherein:
the bridge circuit is further configured to communicate the command sequence comprising a unicast command sequence associated with a unique slave identification (USID) to any one of the plurality of bus slave circuits; and
the controller is further configured to assert the acknowledgement signal on the single-wire bus in response to receiving the unicast command sequence and ind

Assignees

• Qorvo Us Inc

Inventors

• Ngo Christopher Truong
• Hietala Alexander Wayne

Classifications

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F13/20 Primary

  for access to input/output bus · CPC title

• G06F2213/40

  Bus coupling · CPC title