Ldmos transistor and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2022130981-A1
Application number	US-202117508251-A
Country	US
Kind code	A1
Filing date	Oct 22, 2021
Priority date	Oct 23, 2020
Publication date	Apr 28, 2022
Grant date	—

Abstract

A LDMOS transistor and manufacturing method includes: forming an epitaxial layer on a substrate of a first doping type; forming a gate structure on an upper surface of the epitaxial layer; forming a source region of a second doping type in the epitaxial layer, the second doping type is opposite to the first doping type; forming a patterned first insulating layer on the upper surface of the epitaxial layer and the gate structure, and at least exposes part of the source region; forming a first conductive channel by using a sidewall as a mask, the first conductive channel extends from the source region to an upper surface of the substrate so as to connect the source region with the substrate; and forming a drain region of the second doping type in the epitaxial layer.

First claim

What is claimed is:

1 . A method for manufacturing a LDMOS transistor, comprising:
forming an epitaxial layer on a substrate of a first doping type; forming a gate structure on an upper surface of the epitaxial layer; forming a source region of a second doping type in the epitaxial layer, wherein the second doping type is opposite to the first doping type; forming a patterned first insulating layer on the upper surface of the epitaxial layer and the gate structure, wherein the patterned first insulating layer at least comprises a sidewall covering a side surface of the gate structure close to the source region, and at least exposes part of the source region; forming a first conductive channel by using the sidewall as a mask, wherein the first conductive channel extends from the source region to an upper surface of the substrate so as to connect the source region with the substrate; and forming a drain region of the second doping type in the epitaxial layer.

2 . The method according to claim 1 , wherein a step of forming the patterned first insulating layer comprises:
forming a first insulating layer covering the upper surface of the epitaxial layer and an upper surface and the side surface of the gate structure; forming a patterned mask layer on the first insulating layer, wherein the patterned mask layer exposes the first insulating layer above the source region and part of the gate structure; and partially etching the first insulating layer exposed by the patterned mask layer by adopting an etching process to form the sidewall covering the side surface of the gate structure.

3 . The method according to claim 2 , wherein a step of forming the first conductive channel comprises:
self-alignment etching the epitaxial layer to form a first trench by using the sidewall, the gate structure and the patterned mask layer as masks by an etching process; and filling a first conductive material in the first trench to form the first conductive channel.

4 . The method according to claim 3 , wherein part of the sidewall, part of the gate structure, and part of the patterned mask layer are etched while the epitaxial layer is etched.

5 . The method according to claim 4 , wherein a topmost layer of the gate structure comprises a first barrier layer, the epitaxial layer and the first barrier layer having a high etch selectivity.

6 . The method according to claim 5 , wherein prat of the first barrier layer at the topmost layer of the gate structure is at least etched.

7 . The method according to claim 1 , wherein a topmost layer of the gate structure comprises nitride.

8 . The method according to claim 3 , wherein the etching process is an anisotropic etching process.

9 . The method according to claim 3 , wherein further comprising:
forming a body contact region of the first doping type in the substrate exposed by the first trench before filling the first trench, the body contact region being connected to the source region by the first conductive channel.

10 . The method according to claim 4 , wherein further comprising: removing the patterned mask layer remained on the first insulating layer after etching.

11 . The method according to claim 1 , wherein further comprising:
depositing a second conductive material on the first conductive channel, the gate structure, and the patterned first insulating layer, etching part of the second conductive material close to the drain region to form a shielding conductor layer, wherein the shielding conductor layer is electrically connected with the first conductive channel.

12 . The method according to claim 11 , wherein a step of forming the drain region comprises:
depositing a second insulating layer on the shield conductor layer and the patterned first insulating layer; sequentially etching part of the second insulating layer and part of the patterned first insulating layer to form a second trench; and forming the drain region extending from the upper surface of the epitaxial layer to an interior of the epitaxial layer by use of the second trench.

13 . The method according to claim 12 , wherein further comprising: filling the second trench with a third conductive material to form a second conductive channel, and forming a drain electrode on an upper surface of the second insulating layer so that the second conductive channel connects the drain region and the drain electrode.

14 . The method of claim 5 , wherein a step of forming the gate structure comprises:
forming a gate dielectric layer on the upper surface of the substrate, forming a gate conductor on the gate dielectric layer, forming a silicide layer on the gate conductor, forming a third insulating layer on the silicide layer, and forming the first barrier layer on the third insulating layer; and sequentially etching the first barrier layer, the third insulating layer, the silicide layer and the gate conductor to form the gate structure on the upper surface of the substrate.

15 . The method according to claim 1 , wherein before forming the source region, further comprising: doping the first doping type in a first region of the epitaxial layer by taking the gate structure as a mask to form a body region extending from the upper surface of the epitaxial layer to an interior of the epitaxial layer, wherein the source region is located in the body region, and the body region at least partially extends to the epitaxial layer below the gate structure.

16 . The method according to claim 1 , wherein before forming the source region, further comprising: doping the second doping type in a second region of the epitaxial layer by taking the gate structure as a mask to form a drift region extending from the upper surface of the substrate into an interior of the substrate, wherein the drain region is located in the drift region.

17 . The method according to claim 1 , wherein further comprising:
forming a source electrode on a lower surface of the substrate, wherein the source electrode is electrically connected with the source region through the first conductive channel.

18 . An LDMOS transistor comprising:
an epitaxial layer on a substrate of a first doping type; a gate structure on an upper surface of the epitaxial layer; a source region of a second doping type in the epitaxial layer, wherein the second doping type is opposite to the first doping type; a patterned first insulating layer on the upper surface of the epitaxial layer and the gate structure, wherein the patterned first insulating layer at least comprises a sidewall covering a side surface of the gate structure close to the source region; a first conductive channel extending from the source region to an upper surface of the substrate, wherein the source region is connected with the substrate through the first conductive channel; a shield conductor layer covering the first conductive channel and the patterned first insulating layer; and a drain region in the epitaxial layer.

19 . The LDMOS transistor according to claim 18 , wherein the first conductive channel is formed self-aligned by use of the sidewall as a mask.

20 . The LDMOS transistor according to claim 18 , wherein the patterned first insulating layer exposes at least part of an upper surface of the gate structure.

21 . The LDMOS transistor according to claim 18 , wherein the first conductive channel is in contact with prat of a side surface of the sidewall.

22 . The LDMOS transistor according to claim 18 , wherein

Assignees

• Hangzhou Silicon Magic Semiconductor Tech Co Ltd

Inventors

• Wang Jiakun
• Wu Bing

Classifications

• H10W10/051

  of isolation region based on field-effect · CPC title

• H10W10/50

  Isolation regions based on field-effect · CPC title

• H10D64/111 Primary

  Field plates · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title