Amplification apparatus, integration apparatus and modulation apparatus each including duty-cycled resistor

Patent metadata

Field	Value
Publication number	US-2022123700-A1
Application number	US-202117228982-A
Country	US
Kind code	A1
Filing date	Apr 13, 2021
Priority date	Oct 16, 2020
Publication date	Apr 21, 2022
Grant date	—

Abstract

An amplification apparatus includes an amplifier having an inverting terminal, and a non-inverting terminal connected to a reset voltage node, a first capacitor connected to the inverting terminal, an input voltage being applied to the first capacitor, a second capacitor connected to the inverting terminal and an output terminal of the amplifier, and a duty-cycled resistor, connected in parallel to the second capacitor, including a first resistor. The duty-cycled resistor is configured to connect the first resistor and the inverting terminal and to disconnect the first resistor and the reset voltage node during a first time interval included in a period to complete an on-and-off cycle of the duty-cycled resistor, and disconnect the first resistor and the inverting terminal and to connect the first resistor and the reset voltage node during a second time interval included in the period.

First claim

What is claimed is:

1 . An amplification apparatus comprising:
an amplifier having an inverting terminal, and a non-inverting terminal connected to a reset voltage node; a first capacitor connected to the inverting terminal, an input voltage being applied to the first capacitor; a second capacitor connected to the inverting terminal and an output terminal of the amplifier; and a duty-cycled resistor, connected in parallel to the second capacitor, comprising a first resistor, the duty-cycled resistor being configured to
connect the first resistor and the inverting terminal and to disconnect the first resistor and the reset voltage node during a first time interval included in a period to complete an on-and-off cycle of the duty-cycled resistor, and
disconnect the first resistor and the inverting terminal and to connect the first resistor and the reset voltage node during a second time interval included in the period.

2 . The amplification apparatus of claim 1 , wherein
the duty-cycled resistor comprises a first switch and a second switch, the first switch is configured to connect the first resistor and the inverting terminal during the first time interval and to disconnect the first resistor and the inverting terminal during the second time interval, and the second switch is configured to disconnect the first resistor and the reset voltage node during the first time interval and to connect the first resistor and the reset voltage node during the second time interval.

3 . The amplification apparatus of claim 1 , wherein
the duty-cycled resistor comprises a third switch, and the third switch is configured to: connect the first resistor and the inverting terminal during the first time interval; disconnect the first resistor and the inverting terminal during the second time interval; disconnect the first resistor and the reset voltage node during the first time interval; and connect the first resistor and the reset voltage node during the second time interval.

4 . The amplification apparatus of claim 1 , wherein
the first resistor comprises a second resistor and a third resistor, the duty-cycled resistor comprises a fourth switch, a fifth switch, and a sixth switch, the fourth switch is configured to connect the second resistor and the inverting terminal during the first time interval and to disconnect the second resistor and the inverting terminal during the second time interval, the fifth switch is configured to disconnect the second resistor and the reset voltage node during the first time interval and to connect the second resistor and the reset voltage node during the second time interval, and the sixth switch is configured to disconnect the third resistor and the reset voltage node during the first time interval and to connect the third resistor and the reset voltage node during the second time interval.

5 . The amplification apparatus of claim 1 , wherein
the first resistor comprises a second resistor and a third resistor, the duty-cycled resistor comprises a seventh switch and an eighth switch, the seventh switch is configured to: connect the second resistor and the inverting terminal during the first time interval; disconnect the second resistor and the inverting terminal during the second time interval; disconnect the second resistor and the reset voltage node during the first time interval; and connect the second resistor and the reset voltage node during the second time interval, and the eighth switch is configured to: disconnect the third resistor and the reset voltage node during the first time interval; and connect the third resistor and the reset voltage node during the second time interval.

6 . An integration apparatus comprising:
an amplifier having an inverting terminal, and a non-inverting terminal connected to a reset voltage node; a duty-cycled resistor connected to the inverting terminal, an input voltage being applied to the duty-cycled resistor; and a first capacitor connected to the inverting terminal and an output terminal of the amplifier, wherein the duty-cycled resistor comprises a first resistor, wherein the duty-cycled resistor is configured to connect the first resistor and the inverting terminal and to disconnect the first resistor and the reset voltage node during a first time interval included in a period to complete an on-and-off cycle of the duty-cycled resistor, and disconnect the first resistor and the inverting terminal and to connect the first resistor and the reset voltage node during a second time interval included in the period.

7 . The integration apparatus of claim 6 , wherein
the duty-cycled resistor comprises a first switch and a second switch, the first switch is configured to connect the first resistor and the inverting terminal during the first time interval and to disconnect the first resistor and the inverting terminal during the second time interval, and the second switch is configured to disconnect the first resistor and the reset voltage node during the first time interval and to connect the first resistor and the reset voltage node during the second time interval.

8 . The integration apparatus of claim 6 , wherein
the duty-cycled resistor comprises a third switch, and the third switch is configured to: connect the first resistor and the inverting terminal during the first time interval; disconnect the first resistor and the inverting terminal during the second time interval; disconnect the first resistor and the reset voltage node during the first time interval; and connect the first resistor and the reset voltage node during the second time interval.

9 . The integration apparatus of claim 6 , wherein
the first resistor comprises a second resistor and a third resistor, the duty-cycled resistor comprises a fourth switch, a fifth switch, and a sixth switch, the fourth switch is configured to connect the second resistor and the inverting terminal during the first time interval and to disconnect the second resistor and the inverting terminal during the second time interval, the fifth switch is configured to disconnect the second resistor and the reset voltage node during the first time interval and to connect the second resistor and the reset voltage node during the second time interval, and the sixth switch is configured to disconnect the third resistor and the reset voltage node during the first time interval and to connect the third resistor and the reset voltage node during the second time interval.

10 . The integration apparatus of claim 6 , wherein
the first resistor comprises a second resistor and a third resistor, the duty-cycled resistor comprises a seventh switch and an eighth switch, the seventh switch is configured to: connect the second resistor and the inverting terminal during the first time interval; disconnect the second resistor and the inverting terminal during the second time interval; disconnect the second resistor and the reset voltage node during the first time interval; and connect the second resistor and the reset voltage node during the second time interval, and the eighth switch is configured to: disconnect the third resistor and the reset voltage node during the first time interval; and connect the third resistor and the reset voltage node during the second time interval.

11 . A modulation apparatus comprising:
a subtraction circuit to which an input voltage is applied; an amplification circuit, connected to the subtraction circuit, comprising:
an amplifier having an inverting terminal and a non-inverting terminal, the non-inverting terminal connected to a reset voltage node;
a first capacitor connected t

Assignees

• Samsung Electronics Co Ltd
• Korea Advanced Inst Sci & Tech

Inventors

• Lee Wonseok
• Lozada Kent Edrian
• Ryu Seung Tak
• Kim Sang Joon

Classifications

• H03M3/458

  Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

• H03M3/342

  by double sampling, e.g. correlated double sampling · CPC title

• H03F2203/45526

  the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC · CPC title

• H03F2203/45536

  the FBC comprising a switch and being coupled between the LC and the IC · CPC title

• H03F1/34

  Negative-feedback-circuit arrangements with or without positive feedback (H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence {; for rejection of common mode signals H03F3/45479}) · CPC title