Array substrate, liquid crystal display panel and display device

Patent metadata

Field	Value
Publication number	US-2022121057-A1
Application number	US-202217567547-A
Country	US
Kind code	A1
Filing date	Jan 3, 2022
Priority date	Jun 29, 2021
Publication date	Apr 21, 2022
Grant date	—

Abstract

Provided are an array substrate, a liquid crystal display panel and a display device. The array substrate includes a display area and a frame area, where the frame area includes a wiring area; a substrate; multiple signal lines; multiple connection lines, where the multiple connection lines include a first connection line, and the first connection line is located on a side of the signal line facing away from the substrate; a first wire changing layer, which is located between the display area and the wiring area, and is located on a side of the signal line and the connection line facing away from the substrate, the first wire changing layer is electrically connected to the signal line through a first via hole and is electrically connected to the first connection line through a second via hole.

First claim

What is claimed is:

1 . An array substrate, comprising:
a display area and a frame area, wherein the frame area is located on a periphery of the display area and comprises a wiring area; a substrate; a plurality of signal lines, wherein at least part of the plurality of signal lines are located in the display area, and the plurality of signal lines extend in a first direction and are arranged in a second direction, wherein the first direction intersects the second direction; a plurality of connection lines, wherein at least part of the plurality of connection lines are located in the wiring area, and the plurality of connection lines comprises a first connection line, and the first connection line is located on a side of the signal line facing away from the substrate; a first wire changing layer, wherein the first wire changing layer is located between the display area and the wiring area, and the first wire changing layer is located on a side of both the signal line and the connection line facing away from the substrate, and wherein the first wire changing layer is electrically connected to the signal line through a first via hole and is electrically connected to the first connection line through a second via hole; and at least one protection line, wherein in the first direction, the at least one protection line is located between the wiring area and the display area, and the at least one protection line is in a same layer as the first wire changing layer; and wherein a voltage value applied to the signal line is a first voltage, a voltage value applied to the at least one protection line is a second voltage, and the first voltage is greater than or equal to the second voltage.

2 . The array substrate of claim 1 , further comprising:
a first common electrode line, wherein in the first direction, the first common electrode line is located between the first wire changing layer and the display area; and the at least one protection line comprises a first protection line, and in the first direction, the first protection line is located between the first wire changing layer and the first common electrode line.

3 . The array substrate of claim 2 , wherein the at least one protection line further comprises a second protection line, and in the first direction, the second protection line is located between the first wire changing layer and the wiring area;
wherein in the first direction, a width of the first protection line is greater than a width of the second protection line.

4 . The array substrate of claim 1 , further comprising:
a first common electrode line, wherein in the first direction, the first common electrode line is located between the first wire changing layer and the display area; and the at least one protection line comprises a first protection line, and in the first direction, the first protection line is located between the first common electrode line and the display area.

5 . The array substrate of claim 1 , further comprising:
at least one auxiliary line perpendicular to a direction of the substrate, wherein the at least one auxiliary line overlaps the at least one protection line, and the at least one auxiliary line is electrically connected to the at least one protection line through a third via hole.

6 . The array substrate of claim 5 , wherein the at least one auxiliary line comprises a first auxiliary line, and the first auxiliary line is in a same layer as the signal line.

7 . The array substrate of claim 5 , wherein the at least one auxiliary line comprises a second auxiliary line, and the second auxiliary line is in a same layer as the first connection line.

8 . The array substrate of claim 1 , wherein the first wire changing layer and the at least one protection line each comprise a metal oxide.

9 . The array substrate of claim 1 , wherein the plurality of connection lines further comprises a second connection line, and the second connection line is in a same layer as the signal line; and
the first wire changing layer is electrically connected to the signal line through a fourth via hole, and is electrically connected to the second connection line through a fifth via hole.

10 . The array substrate of claim 1 , further comprising:
a first common electrode line, an electrostatic discharge line, and a plurality of first electrostatic discharge circuits; in the first direction, the first common electrode line is located between the first wire changing layer and the display area; the electrostatic discharge line and the plurality of first electrostatic discharge circuits are located between the first common electrode line and the wiring area; a first end of each first electrostatic discharge circuit of the plurality of first electrostatic discharge circuits is electrically connected to the signal line, and a second end of the each first electrostatic discharge circuit is electrically connected to the electrostatic discharge line; the each first electrostatic discharge circuit comprises a plurality of first thin film transistors, wherein each first thin film transistor of the plurality of first thin film transistors comprises a gate, a first electrode, a second electrode and a second wire changing layer, wherein the second wire changing layer is electrically connected to the first electrode of the each first thin film transistor through a sixth via hole and is electrically connected to the gate through a seventh via hole; and the first wire changing layer is in a same layer as the second wire changing layer, and the first wire changing layer, the each first thin film transistor and the second wire changing layer are arranged in the second direction.

11 . The array substrate of claim 1 , further comprising:
a constant voltage low potential line, wherein the constant voltage low potential line is located on a side of the wiring area facing away from the display area and is electrically connected to the at least one protection line.

12 . The array substrate of claim 11 , further comprising:
a step area, wherein the step area and the frame area are located at adjacent two sides of the display area respectively; and wherein the array substrate further comprises a flexible circuit board, and wherein the flexible circuit board is bound to the step area, and the constant voltage low potential line is electrically connected to the flexible circuit board.

13 . The array substrate of claim 11 , further comprising:
a step area, wherein the step area and the frame area are located at adjacent two sides of the display area respectively; and wherein the array substrate further comprises: a display test circuit and a plurality of data lines, wherein the plurality of data lines is located in the display area, the display test circuit is located in the step area and comprises a plurality of second thin film transistors, a plurality of test signal lines and at least one test control line, and wherein each second thin film transistor of the plurality of second thin film transistors comprises a gate, a first electrode and a second electrode, the gate of the each second thin film transistor is electrically connected to the test control line, the first electrode of the each second thin film transistor is electrically connected to the test signal line, and the second electrode of each second thin film transistor is electrically connected to the data line; and the constant voltage low potential line is electrically connected to the test control line.

14 . The array substrate of claim 11 , further comprising:
at least one second electrostatic discharge circuit and a second common electrode

Assignees

• Shanghai Tianma Microelectronics Co Ltd

Inventors

• Wang Cheng
• Zhang Mingwei
• Wang Yu

Classifications

• G02F1/136204

  Arrangements to prevent high voltage or static electricity failures · CPC title

• G02F1/136286

  Wiring, e.g. gate line, drain line · CPC title

• G02F2201/50

  Protective arrangements · CPC title

• G02F1/1345 Primary

  Conductors connecting electrodes to cell terminals · CPC title

• G02F1/13629 Primary

  Multilayer wirings · CPC title