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US-2021043557-A1 · Feb 11, 2021 · US
Method and apparatus to perform operations on multiple segments of a data packet in a network interface controller
US2022116487A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2022116487-A1 |
| Application number | US-202117556089-A |
| Country | US |
| Kind code | A1 |
| Filing date | Dec 20, 2021 |
| Priority date | Dec 20, 2021 |
| Publication date | Apr 14, 2022 |
| Grant date | — |
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- Title
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Abstract
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A stacked memory such as a high bandwidth memory (HBM) with a wide data path is used by a streaming pipeline in a network interface controller to buffer segments of a data packet to allow the network interface controller to perform operations on the packet payload. The headers and packet payload can be scanned and classified concurrently with the buffered payload parsed in parallel.
First claim
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What is claimed is: 1 . A computing device comprising: a memory with a wide data path; and a network interface controller (NIC) communicatively coupled to the memory, the NIC comprising: packet processing circuitry to inspect a first segment of a data packet to determine whether to stream other segments of the data packet or to store the first segment and the other segments of the data packet in the memory to perform operations on the first segment and the other segments of the data packet. 2 . The computing device of claim 1 , wherein the memory is stacked High Bandwidth Memory. 3 . The computing device of claim 1 , wherein the wide data path is 1024 bits. 4 . The computing device of claim 1 , wherein the first segment of the data packet is received by port circuitry in the NIC. 5 . The computing device of claim 1 , wherein the first segment of the data packet is received by host interface circuitry in the NIC. 6 . The computing device of claim 1 , wherein the memory is a first die and the NIC is a second die in a multi-chip package. 7 . The computing device of claim 1 , wherein if the first segment indicates that the operations are not to be performed on the data packet, the other segments of the data packet are streamed directly to port circuitry or host interface circuitry in the NIC. 8 . A system comprising: a processor; and a multi-chip package communicatively coupled to the processor, the multi-chip package comprising: a memory with a wide data path; and a network interface controller (NIC) communicatively coupled to the memory, the NIC comprising: packet processing circuitry to inspect a first segment of a data packet to determine whether to stream other segments of the data packet or to store the first segment and the other segments of the data packet in the memory to perform operations on the first segment and the other segments of the data packet. 9 . The system of claim 8 , wherein the memory is stacked High Bandwidth Memory. 10 . The system of claim 8 , wherein the wide data path is 1024 bits. 11 . The system of claim 8 , wherein the first segment of the data packet is received by port circuitry in the NIC. 12 . The system of claim 8 , wherein the first segment of the data packet is received by host interface circuitry in the NIC. 13 . The system of claim 8 , wherein if the first segment indicates that the operations are not to be performed on the data packet, the other segments of the data packet are streamed directly to port circuitry or host interface circuitry in the NIC. 14 . The system of claim 8 , further comprising: a power supply to provide power to the system. 15 . A method comprising: receiving, by packet processing circuitry in a network interface controller (NIC) a first segment of a data packet; and determining, by the packet processing circuitry, based on an inspection of the first segment of the data packet whether to stream other segments of the data packet or to store the first segment and the other segments of the data packet in a memory with a wide data path communicatively coupled to the network interface controller to perform operations on the first segment and the other segments of the data packet. 16 . The method of claim 15 , wherein the memory is stacked High Bandwidth Memory. 17 . The method of claim 15 , wherein the wide data path is 1024 bits. 18 . The method of claim 15 , wherein the first segment of the data packet is received by port circuitry in the NIC. 19 . The method of claim 15 , wherein the first segment of the data packet is received by host interface circuitry in the NIC. 20 . The method of claim 15 , wherein the memory is a first die and the NIC is a second die in a multi-chip package. 21 . The method of claim 15 , wherein if the first segment indicates that the operations are not to be performed on the data packet, the other segments of the data packet are streamed directly to port circuitry or host interface circuitry in the NIC.
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- What does patent US2022116487A1 cover?
- A stacked memory such as a high bandwidth memory (HBM) with a wide data path is used by a streaming pipeline in a network interface controller to buffer segments of a data packet to allow the network interface controller to perform operations on the packet payload. The headers and packet payload can be scanned and classified concurrently with the buffered payload parsed in parallel.
- Who is the assignee on this patent?
- Intel Corp
- What technology area does this patent fall under?
- Primary CPC classification H04L69/22. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Apr 14 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).