Dcdc converters

US2022115950A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2022115950-A1
Application numberUS-202117500629-A
CountryUS
Kind codeA1
Filing dateOct 13, 2021
Priority dateOct 14, 2020
Publication dateApr 14, 2022
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A circuit portion comprises a DCDC converter that provides current from an output to a plurality of loads. Channel logic circuitry is configured to provide current from the output of the converter to each load according to a cyclical sequence, wherein each cycle has a duration that is divided equally into a plurality of time slots. The channel logic circuitry is configured to provide current to each load for one or more discrete time slots. The number of time slots is greater than the number of loads so that at least two output loads receive current for different numbers of time slots in a cycle.

First claim

Opening claim text (preview).

1 . A circuit portion comprising: a DCDC converter arranged to provide current from an output of the converter to a plurality of output loads; and channel logic circuitry configured to provide current cyclically from the output of the converter to each of the plurality of output loads according to a sequence that is repeated for a plurality of cycles, wherein the channel logic circuitry is configured to select the sequence, from a plurality of predetermined sequence options, according to operating characteristics of one or more of the plurality of output loads; and wherein: each cycle has a cycle duration; the cycle duration is divided equally into a plurality of time slots; the channel logic circuitry is configured to provide current to each of the plurality of output loads for the duration of one or more discrete time slots; and the number of time slots is greater than the number of output loads so that at least two output loads receive current for different numbers of time slots in a cycle. 2 . The circuit portion of claim 1 , wherein the DCDC converter is configured to operate in discontinuous-conduction-mode 3 . The circuit portion of claim 1 , wherein the channel logic circuitry is configured to change which of the plurality of output loads receives the output current at each time slot transition. 4 . The circuit portion of claim 1 , wherein the channel logic circuitry is configured to generate or to modify the sequence during operation of the circuit. 5 . The circuit portion of claim 1 , wherein the circuit portion comprises a power monitor arranged to monitor loading of one or more of the plurality of output loads. 6 . The circuit portion of claim 5 , wherein the channel logic circuitry is arranged to modify the sequence according to a signal received from the power monitor. 7 . The circuit portion of claim 6 , wherein the sequence is selected by the channel logic circuitry from a lookup table according to the value of the received signal. 8 . The circuit portion of claim 1 , wherein the circuit portion further comprises a pulse width modulation module arranged to control operation of the DCDC converter. 9 . The circuit portion of claim 8 , wherein the pulse width modulation module comprises duty control logic, configured to activate and deactivate low side and high side switches of the DCDC converter such that an inductor of the DCDC converter is both charged and discharged within one time slot. 10 . The circuit portion of claim 9 , wherein the pulse width modulation module is configured to activate and deactivate the low side and high side switches of the DCDC converter such that the inductor of the DCDC converter is charged and discharged no more than once per time slot.

Assignees

Inventors

Classifications

  • H02M3/1588Primary

    comprising at least one synchronous rectifier element (H02M3/1582, H02M3/1584 take precedence) · CPC title

  • H02M3/158Primary

    including plural semiconductor devices as final control devices for a single load · CPC title

  • having two or more independently controlled outputs (for DC-DC converter with intermediate AC H02M3/33561) · CPC title

  • using bucking or boosting DC sources · CPC title

  • with digital control · CPC title

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Frequently asked questions

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What does patent US2022115950A1 cover?
A circuit portion comprises a DCDC converter that provides current from an output to a plurality of loads. Channel logic circuitry is configured to provide current from the output of the converter to each load according to a cyclical sequence, wherein each cycle has a duration that is divided equally into a plurality of time slots. The channel logic circuitry is configured to provide current to…
Who is the assignee on this patent?
Nordic Semiconductor Asa
What technology area does this patent fall under?
Primary CPC classification H02M3/1588. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Apr 14 2022 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).