Chip card body, method for forming a chip card body and chip card

Patent metadata

Field	Value
Publication number	US-2022115311-A1
Application number	US-202117498828-A
Country	US
Kind code	A1
Filing date	Oct 12, 2021
Priority date	Oct 13, 2020
Publication date	Apr 14, 2022
Grant date	—

Abstract

A chip card body including a metal plate having at least one slot which defines a current flow path on the metal plate, and having a coupling region to accommodate a chip with an antenna, wherein the coupling region is configured to inductively couple the metal plate to the antenna of the chip, a dielectric layer applied to the metal plate, an electrically conductive layer applied to a side of the dielectric layer opposite the metal plate, and at least one electrically conductive coupling between the metal plate and the electrically conductive layer, wherein the metal plate, the dielectric layer and the electrically conductive layer form a capacitor.

First claim

1 . A chip card body, comprising:
a metal plate having at least one slot which defines a current flow path on the metal plate, and having a coupling region configured to accommodate a chip with an antenna, and configured to inductive couple the metal plate to the antenna of the chip; a dielectric layer applied to the metal plate; and a first electrically conductive layer applied to a side of the dielectric layer opposite the metal plate; and at least one electrically conductive coupling between the metal plate and the electrically conductive layer, wherein the metal plate, the dielectric layer, and the first electrically conductive layer form a capacitor.

2 . A chip card body, comprising:
a metal plate having at least one slot which defines a current flow path on the metal plate, and having a coupling region configured to receive a chip with an antenna, and configured to inductively couple the metal plate with the antenna of the chip; a dielectric layer applied to the metal plate; a first electrically conductive layer applied to a side of the dielectric layer opposite the metal plate; a second dielectric layer on the first electrically conductive layer; and a second electrically conductive layer on the second dielectric layer; an electrically conductive coupling between the metal plate and the first electrically conductive layer; and a second electrically conductive coupling between the metal plate and the second electrically conductive layer, wherein the first electrically conductive layer, the second dielectric layer, and the second electrically conductive layer form a capacitor.

3 . The chip card body as claimed in claim 1 ,
wherein the first electrically conductive layer comprises a main capacitor region and at least one tuning region, and wherein the at least one tuning region is connected to the main capacitor region only by means of a narrow connecting region so that the tuning region is separable from the main capacitor region by cutting through the connecting region.

4 . The chip card body as claimed in claim 3 ,
wherein the connecting region has a width not exceeding one tenth of the circumference of the first electrically conductive layer.

5 . The chip card body as claimed in claim 2 ,
wherein the second electrically conductive layer comprises a main capacitor region and at least one tuning region, and wherein the at least one tuning region is connected to the main capacitor region only by means of a narrow connecting region so that the tuning region can be separated from the main capacitor region by cutting through the connecting region.

6 . The chip card body as claimed in claim 5 ,
wherein the connecting region has a width not exceeding one tenth of the circumference of the second electrically conductive layer.

7 . The chip card body as claimed in claim 1 ,
wherein the first electrically conductive layer comprises at least one slot.

8 . The chip card body as claimed in claim 7 ,
wherein the at least one slot of the first electrically conductive layer extends above the slot of the metal plate.

9 . A method for forming a chip card body, the method comprising:
forming at least one slot in a metal plate in such a way that a current flow path is defined on the metal plate and a coupling region is formed for receiving a chip with an antenna, wherein the coupling region is configured to inductively couple the metal plate to the antenna of the chip; applying a dielectric layer to the metal plate; applying an electrically conductive layer to a side of the dielectric layer opposite the metal plate; and electrically conductively coupling the metal plate and the electrically conductive layer, wherein the metal plate, the dielectric layer, and the electrically conductive layer form a capacitor.

10 . A method for forming a chip card body, the method comprising:
forming at least one slot in a metal plate in such a way that a current flow path is defined on the metal plate and a coupling region is configured to receive a chip with an antenna, and is configured to inductively couple the metal plate to the antenna of the chip; applying a dielectric layer to the metal plate; applying an electrically conductive layer to a side of the dielectric layer opposite the metal plate; applying a second dielectric layer to the electrically conductive layer; applying a second electrically conductive layer to the second dielectric layer; electrically conductively coupling the metal plate and the electrically conductive layer; and electrically conductively coupling the metal plate and the electrically conductive layer, wherein the electrically conductive layer plate, the second dielectric layer, and the second electrically conductive layer form a capacitor.

11 . The method as claimed in claim 9 , further comprising:
laminating the dielectric layer onto the metal plate.

12 . The method as claimed in claim 10 , further comprising:
laminating the dielectric layer onto the metal plate.

13 . The method as claimed in claim 9 , further comprising:
simultaneously laminating the dielectric layer and the electrically conductive layer.

14 . The method as claimed in claim 10 , further comprising:
simultaneously laminating the dielectric layer and the electrically conductive layer.

15 . The method as claimed in claim 10 , further comprising:
laminating the second dielectric layer onto the metal plate.

16 . The method as claimed in claim 15 , further comprising:
laminating the second electrically conductive layer onto the dielectric layer.

17 . The method as claimed in claim 10 , further comprising:
simultaneously laminating the second dielectric layer and the second electrically conductive layer.

18 . The method as claimed in claim 10 , further comprising:
simultaneously laminating the dielectric layer, the electrically conductive layer, the second dielectric layer, and the second electrically conductive layer.

19 . A chip card, comprising:
a chip card body as claimed in claim 1 ; and a chip accommodated in the coupling region and having an antenna.

Assignees

• Infineon Technologies Ag

Inventors

• Pachler Walther
• Huber Michael
• Pohl Jens
• Tompa-Antal Szabolcs

Classifications

• H10W70/6875

  being on a metallic substrate, e.g. insulated metal substrates [IMS] · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W70/685 Primary

  comprising multiple insulating layers · CPC title

• G06K19/02 Primary

  characterised by the selection of materials, e.g. to avoid wear during transport through the machine · CPC title